Artesyn Embedded Technology ATCA-7370, Installation And Use Manual

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Maps and Registers
ATCA-7370/ATCA-7370-S Installation and Use (6806800P54G )
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6.1.3 Non-Maskable Interrupt Generation
Non-Maskable Interrupt (NMI) is used to force a non-Maskable interrupt to the processor. The
processor detects an NMI when it detects a rising edge on NMI. NMI is reset by setting the
corresponding NMI source enable/disable bit in the NMI Status and Control register (I/O
Register 61h).
The chipset can generate NMI by several sources which are described in following table.
The GPIO[15:0] can generate NMI. On the ATCA-7370, the GPIO3 of PCH connects to the
FPGA. The IPMC can request an NMI interrupt through controlling the GPIO3 of PCH connect
to FPGA.
Table 6-4 NMI Sources
Cause of NMI Comment
SERR# goes active (either internally, externally
using SERR# signal, or using message from
processor) Can instead be routed to generate an SCI through
the NSI2SCI_EN bit (Device 31: Function 0, TCO
Base + 08h, Bit 11).
IOCHK# goes active using SERIRQ# stream (ISA
System Error) Can instead be routed to generate an SCI through
the NMI2SCI_EN bit (Device 31: Function 0, TCO
Base + 08h, Bit 11).
SECSTS Register Device 31: Function F0 Offset
1Eh, Bit 8. This is enabled by the Parity Error Response Bit
(PER) at Device 30: Function 0 Offset 04, Bit 6.
DEV_STS Register Device 31: Function F0 Offset
06h, Bit 8
GPIO[15:0] When configured as a General
Purpose input and routed as NMI (by GPIO_ROUT
at Device 31: Function 0 Offset B8)