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Specifications

ARM DUI 0447J

B-4

ID052914

Non-Confidential

B.1.3

SMB asynchronous read

Figure B-3

shows the asynchronous read timing.

Figure B-3 Asynchronous read timing

The intervals are as follows:
•

Tsmbis

= 6ns

•

Tsmbov

= 7.5ns

•

Tsmboh

Tperiod

•

Tsmbfov

= 6ns

•

Tsmbfis

= 6ns

All SMB input signals are registered on the rising edge of

SMB_CLKO

. They are then

registered a second time before being output on the IOFPGA SMB bus. This adds 1.5 clock
cycles of latency.

All IOFPGA SMB input signals are registered on the rising edge of

SMB_CLKO

. They are

then registered a second time before being output to the SMB bus. This adds 2 clock cycles of
latency.

An asynchronous read has a penalty of 1.5 clock cycles for the control signals to leave the IO
FPGA and an additional 2 clocks for the read data to be passed back. The total delay is 3.5 clock
cycles.

B.1.4

SMB asynchronous write

Figure B-4 on page B-5

shows the asynchronous write timing.

RDATA

SMB_DATA

SMB_nOE

SMB_nCS

SMB_ADDR

ADDR

SMB_CLKO

SMB_nCSreg_in

SMBF_nCS

RDATA

SMBF_DATA

RDATA

SMBF_DATAreg_in

RDATA

SMB_DATAinternal

SMBF_nOE

Tsmb

Trc

Tsmb

Tsmbf

Tsmb

Summary of Contents for Express uATX

Page 2: ... use of the product ARM shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information or any incorrect use of the product Where the term ARM is used it means ARM or any of its subsidiaries as appropriate Confidentiality Status This document is Non Confidential The right to use copy and disclose this document may be ...

Page 3: ...ns However there is no guarantee that interference will not occur in a particular installation If this equipment causes harmful interference to radio or television reception which can be determined by turning the equipment off or on you are encouraged to try to correct the interference by one or more of the following measures ensure attached cables do not lie across the card reorient the receiving...

Page 4: ... 2 Hardware Description 2 1 Motherboard architecture and buses 2 2 2 2 Power up on off and reset signals 2 6 2 3 Clock architecture 2 9 2 4 Power 2 11 2 5 Peripherals and interfaces on the motherboard 2 12 2 6 Interrupt signals 2 18 2 7 DMA signals 2 20 2 8 JTAG and test connectors 2 21 Chapter 3 Configuration 3 1 Configuration environment 3 2 Chapter 4 Programmers Model 4 1 About this programmers...

Page 5: ...v ID052914 Non Confidential 4 5 IO Peripherals and interfaces 4 26 Appendix A Signal Descriptions A 1 Audio CODEC interface A 2 A 2 UART interface A 3 Appendix B Specifications B 1 Timing specifications B 2 B 2 Electrical Specification B 7 Appendix C Revisions ...

Page 6: ...2009 2014 ARM All rights reserved vi ID052914 Non Confidential Preface This Technical Reference Manual TRM is for the Motherboard Express µATX It contains the following sections About this book on page vii Feedback on page xi ...

Page 7: ... use with this motherboard Using this book This book is organized into the following chapters Chapter 1 Introduction Read this for an overview of the motherboard Chapter 2 Hardware Description Read this for a description of the hardware present on the motherboard Chapter 3 Configuration Read this for a description of the configuration process Chapter 4 Programmers Model Read this for a description...

Page 8: ...tead of the full command or option name monospace italic Denotes arguments to monospace text where the argument is to be replaced by a specific value monospace bold Denotes language keywords when used outside example code and Enclose replaceable terms for assembler syntax where they appear in code or code fragments For example MRC p15 0 Rd CRn CRm Opcode_2 Timing diagrams The figure named Key to t...

Page 9: ...m com for embedded software development resources including the Cortex Microcontroller Software Interface Standard CMSIS ARM publications This book contains information that is specific to this product The following publications are open access documents that provide information about ARM Systems IP peripherals and controllers used in the motherboard ARM PrimeCell PS2 Keyboard Mouse Interface PL05...

Page 10: ...ical Reference Manual ARM DDI 0498 ARM Versatile Express Configuration Technical Reference Manual ARM DDI 0496 ARM Versatile Express Boot Monitor Reference Manual ARM DUI 0465 RealView Debugger User Guide ARM DUI 0153 RealView ICE and RealView Trace User Guide ARM DUI 0155 RealView Compilation Tools Developer Guide ARM DUI 0203 RealView Compilation Tools Compilers and Libraries Guide ARM DUI 0205 ...

Page 11: ...pplier and give The product name The product revision or version An explanation with as much information as you can provide Include symptoms and diagnostic procedures if appropriate Feedback on content If you have comments on content then send an e mail to errata arm com Give the title the number ARM DUI 0447J the page numbers to which your comments apply a concise explanation of your comments ARM...

Page 12: ...ARM All rights reserved 1 1 ID052914 Non Confidential Chapter 1 Introduction This chapter introduces the Motherboard Express µATX It contains the following sections About the Motherboard Express µATX on page 1 2 Precautions on page 1 5 ...

Page 13: ...ards simplify software development and porting Automatic detection and configuration of attached CoreTile Express and LogicTile Express daughterboards Automatic shutdown for over temperature or power supply failure System is unable to power up if the daughterboards cannot be configured Power sequencing of system Supports drag and drop file update of configuration files Uses either a 12V power supp...

Page 14: ...ser LEDs ATX PSU connector with plug from enclosure connector CoreTile Express daughterboard LogicTile Express daughterboard Micro SDCard configuration memory D0 OTGON USB2ON USB3ON 5VOK 3 3VOK SB D7 ILA Battery MCC RTCC Back panel connectors Manufacturing Test Debug JTAG to Core Tile Express USB status LEDs Test ILA Voltage status LEDs Case fan 12V ...

Page 15: ... power on and USB B activity Compact Flash connector Figure 1 2 ATX back panel Note There are two reset buttons ON OFF Soft Reset This is colored red and is a system power ON OFF and Software Reset push button Hardware RESET This is colored black and is a Hardware Reset push button You can use both push buttons to put the system into Standby State but only the ON OFF button can power up the system...

Page 16: ...ge The motherboard is intended for use in a laboratory or engineering development environment If removed from its enclosure the board becomes more sensitive to electrostatic discharges and generates increased electromagnetic emissions Removing the board from the enclosure also results in flexing that fractures the printed circuit board connections to the components Caution To avoid damage observe ...

Page 17: ...the Motherboard Express µATX It contains the following sections Motherboard architecture and buses on page 2 2 Power up on off and reset signals on page 2 6 Clock architecture on page 2 9 Power on page 2 11 Peripherals and interfaces on the motherboard on page 2 12 Interrupt signals on page 2 18 DMA signals on page 2 20 JTAG and test connectors on page 2 21 ...

Page 18: ...the source for the audio and video signals to the DVI connector Two daughterboard slots one for a CoreTile Express board and one for LogicTile Express board CoreTile Express daughterboard site 1 LogicTile Express daughterboard site 2 HDRY HDRX Motherboard Express μATX HDRY1 HDRX1 HDRY2 HDRX2 HDRX HDRY SB MMB SMB Motherboard IO FPGA SB Test chip Daughterboard Configuration Controller Motherboard Co...

Page 19: ...ss Gen 1 slots each supporting four lanes MMC SD card slot Compact Flash slot Four UARTs Three USB interfaces providing one OTG slave and two standard USB 2 0 host ports DVI connector with analogue and digital video support at 1080p I2S SPDIF digital audio support for HDMI Ethernet interface PS2 Keyboard and Mouse AC97 Audio CODEC with Audio in Audio out and MIC in USB B configuration port that ac...

Page 20: ...eripheral and memory accesses from the daughterboards to the motherboard A Static Memory Controller in the daughterboard outputs chip select signals to access memory and peripherals on the motherboard The memory controller determines the base address for each chip select See IO Peripherals and interfaces on page 4 26 Note Site 2 has limited access to the motherboard Site 2 can only access the moth...

Page 21: ...herboard See the documentation for your daughterboard PCIe Bus The motherboard supports four PCI Express PCIe slots x4 x4 x8 and x16 connector sizes each with a lane width of four A PCI Express switch connects these slots to the daughterboards over the PCIe bus that has eight lanes to each daughterboard See Figure 2 1 on page 2 2 for more information Note The V2M P1 motherboard supports a root com...

Page 22: ...als Note To completely power down the system you must turn off the external 12V power supply See also the ARM Versatile Express Configuration Technical Reference Manual for an overview of the startup sequence and the operation of the ON OFF Soft Reset and Hardware Reset push button switches Test chip Motherboard Express μATX CoreTile Express daughterboard site 1 Daughterboard Configuration Control...

Page 23: ...e Caution If the ON OFF Soft Reset switch is pressed and held for more than two seconds the system enters the Standby State in the same way as pressing the black Hardware RESET push button 2 The MCC asserts the CB_nRST reset signal Depending on the setting of ASSERTNPOR in the generic configuration file config txt CB_nPOR might also be asserted 3 The daughterboards and IO FPGA are reset 4 The MCC ...

Page 24: ...SERTNPOR in the generic configuration file config txt CB_nPOR might also be asserted Note If only CB_nRST is asserted a soft reset is performed The MCC and Daughterboard Configuration Controller reset the devices in the system but do not perform a full re initialization If only CB_nPOR is also asserted a hard reset is performed The MCC and Daughterboard Configuration Controller perform a full re i...

Page 25: ...tching in run mode Method 1 requires a reset to become effective Figure 2 3 on page 2 10 shows an overview of the clocks in a typical Versatile Express system Table 2 1 Motherboard clocks Oscillator Default Description Range OSC0 50MHz MCC static memory clock The MCC uses this clock for accesses to the SMB before control of the SMB buses is passed to the daughterboards After configuration each dau...

Page 26: ...oard Site 2 Test chip Daughterboard Configuration Controller FPGA TC reference clock CLCD clock HDRY HDRX MCC External AXIM clock External AXIS clock M S MMB clocks PCI reference clock SMB clock HSB S AXI clock logic HDRY HDRY2 HDRX1 HDRX HDRX2 MMB clocks PCI reference clock SMB clock SMB feedback SMB feedback I O and multiplexer FPGAs PCI Express clock generator Clock generators To PCI Express sl...

Page 27: ...erboard that supply fixed voltages to the motherboard and attached daughterboards All daughterboards are supplied with 5V for internal supply generation If the daughterboard requires additional supply voltages a separate power supply connector must supply them VIO The SMB SB and MMB buses operate over the range 0 8 3 3 volts These buses must operate at the same voltage that is supplied from the mo...

Page 28: ...miconductor LM4549 audio CODEC CLCD controller A PL111 PrimeCell CLCD controller is present in the FPGA You can implement a separate CLCD controller in an attached Logic Tile The Multiplexer FPGA selects between the FPGA CLCD controller and the CLCD signals from the daughterboards See DVI multiplexer on page 2 15 and Color LCD Controller on page 4 27 Compact Flash The IO FPGA contains a custom Com...

Page 29: ... options or displaying status information See User Switch Register on page 4 10 and LED Register on page 4 11 Watchdog The ARM SP805 Watchdog module can apply a reset to a system in the event of a software failure See Watchdog on page 4 40 Figure 2 4 shows the IO interfaces using the ARM Legacy memory map see Memory maps on page 4 3 Figure 2 4 Architectural block diagram of IO FPGA using the ARM L...

Page 30: ...MC bus interface to an external Philips ISP1761 USB 2 0 controller Three USB interfaces are provided on the motherboard USB port 1 provides an OTG device interface and connects to the mini USB connector on the back panel of the enclosure USB port 2 and USB port 3 can function in either master or slave mode and connect to the dual A Type connector on the rear panel of the enclosure USB port 2 is th...

Page 31: ...udio interfaces from the motherboard and two daughterboards respectively to the DVI connector on the back panel This means you can select either of the daughterboards or the IO FPGA to drive the DVI connector Figure 2 6 shows how the Multiplexer FPGA interfaces with the daughterboards IO FPGA and the Motherboard Configuration Controller MCC The DVI controller is an Sil9022 and supports up to 1080p...

Page 32: ...ng the config txt file By default the daughterboard in Site 1 is the root complex The V2M P1 motherboard does not support an endpoint either on the daughterboard in Site 1 or the daughterboard in Site 2 The PCIe slots are the only endpoints and conform to the PCI Express 1 0 specification There is no PCIe endpoint in the motherboard IO FPGA Because there are no PCIe lanes connected to the motherbo...

Page 33: ...oard CoreTile Express daughterboard x4 x8 x8 Motherboard Configuration Controller MCC x4 x4 x4 PCIe1 PCIe2 HDRY Test chip with End Point or Root Complex FPGA with End Point or Root Complex HDRY1 HDRY2 HDRY PCI Express Switch 32 lanes 6 ports PCI Express slot x16 4 lanes Slot x 8 4 lanes Slot x 4 4 lanes Slot x4 4 lanes IO FPGA SMB2 SMB1 I2C Resets Serial bus interface Reset and configuration logic...

Page 34: ...ed to the daughterboards on signals IRQ 39 36 and IRQ 35 32 The function of these is determined by the daughterboard Figure 2 8 shows the interrupt architecture Figure 2 8 Interrupt architecture For more information on interrupt handling see the documentation for your CoreTile Express daughterboard Table 2 2 shows the interrupt mapping for the IRQ 47 0 signals Motherboard Express μATX LogicTile Ex...

Page 35: ...t 12 KMI0_INTR Keyboard Mouse interrupt 13 KMI1_INTR Keyboard Mouse interrupt 14 CLCDINTR Display interrupt 15 ETH_INTR Ethernet interrupt 16 USB_INT USB interrupt 17 PCIE_GPEN PCI Express interrupt 21 18 SB1_INT 3 0 Copy of interrupts SB_IRQ 35 32 25 22 SB2_INT 3 0 Copy of interrupts SB_IRQ 39 36 31 26 Reserved 35 32 SB1_INT 3 0 Reserved interrupts INT 3 0 from Site 1 daughterboard 39 36 SB2_INT ...

Page 36: ...ACK 1 0 also connect to the motherboard IO FPGA These are only used for handshaking between the two selected peripherals in the IO FPGA and a DMAC in one of the daughterboard sites See Figure 2 9 The motherboard IO FPGA implements a DMA router that selects two DMAC capable motherboard peripherals for connection to the DMAC pins on one of the daughterboard sites You must ensure that only one daught...

Page 37: ...plication code connect a debugger to the JTAG connector on the CoreTile Express daughterboard Note For convenience you can connect the JTAG connector on the CoreTile Express daughterboard to the JTAG connector on the back panel Caution The Motherboard Express µATX contains several connectors used for manufacturing test The manufacturing test connectors must not be used Connecting to them might dam...

Page 38: ... reserved 3 1 ID052914 Non Confidential Chapter 3 Configuration This chapter describes the configuration sequence for the Motherboard Express µATX and any attached daughterboards It contains the following section Configuration environment on page 3 2 ...

Page 39: ...Configuration microSD card or Universal Serial Bus Mass Storage Device USBMSD on the Motherboard Express V2M P1 Configuration EEPROM on the Motherboard Express V2M P1 ON OFF Soft Reset and Hardware RESET buttons on the on the Motherboard Express V2M P1 USB B port on the Motherboard Express V2M P1 Four UART ports on the Motherboard Express V2M P1 NOR flash on the Motherboard Express V2M P1 microSD ...

Page 40: ...n the Motherboard Express V2M P1 CoreTile Express and LogicTile Express daughterboards See the ARM Versatile Express Configuration Technical Reference Manual and the Technical Reference Manuals for the attached daughterboards for specific information on the configuration environment of your Versatile Express system and also for information on Power on sequence Push button and remote resets Configu...

Page 41: ... This chapter describes the memory map and the configuration registers for the peripherals on the motherboard It contains the following sections About this programmers model on page 4 2 Memory maps on page 4 3 Register summary on page 4 8 Register descriptions on page 4 10 IO Peripherals and interfaces on page 4 26 ...

Page 42: ...tion The offset of each register from the base address is fixed Do not attempt to access reserved or unused address locations Attempting to access these locations can result in Unpredictable behavior Unless otherwise stated in the accompanying text Do not modify undefined register bits Ignore undefined register bits on reads All register bits are reset to a logic 0 by a system or power on reset Ac...

Page 43: ... Express A9x4 daughterboard Figure 4 1 Legacy system memory map as viewed from a CoreTile Express A9x4 daughterboard Caution The attached daughterboard defines the address ranges for the SMB chip selects Daughterboard local memory aliased from 0x80000000 0x00000000 Daughterboard 0x10000000 Motherboard memory and peripherals SMB CS0 to CS6 Daughterboard 0xE0000000 Daughterboard HSB AXI buses 0xFFFF...

Page 44: ...PL050 CS7 0x00007000 0x00007FFF Reserved CS7 0x00008000 0x00008FFF UART0 ARM PL011 CS7 0x00009000 0x00009FFF UART1 ARM PL011 CS7 0x0000A000 0x0000AFFF UART2 ARM PL011 CS7 0x0000B000 0x0000BFFF UART3 ARM PL011 CS7 0x0000C000 0x0000CFFF Reserved CS7 0x0000D000 0x0000EFFF WDT SP805 CS7 0x0000F000 0x0000FFFF Reserved CS7 0x00010000 0x00010FFF TIMER0 1 ARM SP804 CS7 0x00011000 0x00011FFF TIMER2 3 ARM S...

Page 45: ... defines the address ranges for the SMB chip selects Reserved CS3 0x00800000 0x01FFFFFF Ethernet SMSC LAN9118 CS3 0x02000000 0x02FFFFFF USB Philips ISP1761 CS3 0x03000000 0x03FFFFFF Table 4 1 Motherboard peripheral ARM legacy memory map continued Peripheral Interface logic SMB chip select Address offset Motherboard memory and peripherals SMB CS0 to CS6 Daughterboard test chip peripherals Daughterb...

Page 46: ...FFFFF USB CS2 0x03000000 0x03FFFFFF Local DAP ROM CS3 0x00000000 0x0000FFFF System registers Custom CS3 0x00010000 0x0001FFFF System control ARM SP810 CS3 0x00020000 0x0002FFFF Serial Bus PCI Custom CS3 0x00030000 0x0003FFFF AACI ARM PL041 CS3 0x00040000 0x0004FFFF MMCI ARM PL180 CS3 0x00050000 0x0005FFFF KMI0 ARM PL050 CS3 0x00060000 0x0006FFFF KMI0 ARM PL050 CS3 0x00070000 0x0007FFFF Reserved CS...

Page 47: ...terboard Reserved CS3 0x00150000 0x0015FFFF Serial Bus DVI Custom CS3 0x00160000 0x0016FFFF RTC ARM PL031 CS3 0x00170000 0x0017FFFF Reserved CS3 0x00180000 0x0018FFFF Reserved CS3 0x00190000 0x0019FFFF Compact Flash Custom CS3 0x001A0000 0x001AFFFF UART4 ARM PL011 CS3 0x001B0000 0x001BFFFF Reserved CS3 0x001C0000 0x001CFFFF Reserved CS3 0x001D0000 0x001DFFFF Reserved CS3 0x001E0000 0x001EFFFF CLCD...

Page 48: ...n Unpredictable behavior Table 4 3 shows the registers in offset order from the base memory address Table 4 3 Register map for status and system registers Offset Value Register Type Reset Description 0x0000 SYS_ID RO RWa 0xX190XXXXb System Identifier See ID Register on page 4 10 0x0004 SYS_SW RO RWa 0xX00000XXb Bits 7 0 are the soft user switches See User Switch Register on page 4 10 0x0008 SYS_LE...

Page 49: ...eserved RO 0x00000000 0x0084 SYS_PROCID0 RW 0x0X000XXXb See SYS_ PROCID0 Register on page 4 18 0x0088 SYS_PROCID1 RW 0x0X000XXXb See SYS_PRODCID1 Register on page 4 19 0x008C 0x009C Reserved RW 0x00000000 0x00A0 SYS_CFGDATA RW 0x00000000 See System Configuration registers on page 4 21 0x00A4 SYS_CFGCTRL RW 0x00000000 See Configuration Control Register on page 4 22 0x00A8 SYS_CFGSTAT RW 0x00000000 ...

Page 50: ...ignments The register value depends on the image loaded into the FPGA 4 4 2 User Switch Register The SYS_SW Register characteristics are Purpose Reads the USERSWITCH entry in the config txt file A value of 1 indicates that the switch is on Usage constraints See Table 4 5 on page 4 11 FPGA Rev 31 28 27 16 15 12 11 8 7 0 HBI Build Arch Table 4 4 SYS_ID Register bit assignments Bits Access Name Reset...

Page 51: ...5 SYS_SW Register bit assignments Bits Access Name Reset Description 31 Read only SW 1 Indicates the value of physical configuration switch SW 1 See the ARM Versatile Express Configuration Technical Reference Manual 30 Read only SW 0 Indicates the value of physical configuration switch SW 0 See the ARM Versatile Express Configuration Technical Reference Manual 29 Read only nUART0CTS UART0 control ...

Page 52: ...ints Configurations Available in all configurations Attributes See Table 4 3 on page 4 8 Table 4 7 shows the bit assignments 4 4 5 Flag Registers The SYS_ Registers characteristics are Purpose Provides two 32 bit register locations containing general purpose flags You can assign any meaning to the flags Usage constraints There are no usage constraints Configurations Available in all configurations...

Page 53: ...changed Flag and Nonvolatile Flag Clear Registers Use the SYS_FLAGSCLR and SYS_NVFLAGSCLR registers to clear bits in the SYS_FLAGS and SYS_NVFLAGS registers Write 1 to CLEAR the associated flag Write 0 to leave the associated flag unchanged 4 4 6 MCI Register The SYS_MCI Register characteristics are Purpose Provides status information on the MultiMedia card socket Usage constraints There are no us...

Page 54: ...memory devices Usage constraints There are no usage constraints Configurations Available in all configurations Attributes See Table 4 3 on page 4 8 Figure 4 7 shows the bit assignments Figure 4 7 SYS_FLASH Register bit assignments 0 31 WPROT 1 2 Undefined CARDIN Table 4 9 SYS_MCI Register bit assignments Bits Name Reset Description 31 2 0x0000000 Undefined write ignored read as zero 1 WPROT bx Sta...

Page 55: ...s Bits Name Reset Description 31 1 0x0000000 Undefined write ignored read as zero 0 FLASHWPn b0 b0 Enables the Lock Down mechanism The Lock Down Block command puts the NOR Flash memory blocks into read only state The blocks cannot be reprogrammed erased or unlocked b1 Overrides the Lock Down mechanism The Unlock Block command can unlock previously locked down NOR Flash memory blocks Note Power on ...

Page 56: ...neous flags related to communication Usage constraints See Table 4 13 on page 4 17 Configurations See Table 4 13 on page 4 17 Attributes See Table 4 3 on page 4 8 Figure 4 3 on page 4 10 shows the bit assignments Figure 4 9 SYS_MISC Register bit assignments Table 4 12 SYS_24MHz Register bit assignments Bits Name Reset Description 31 0 SYS_24MHz The register is set to zero by a CB_nRST reset then c...

Page 57: ...these bits LOW enables control of ISP1761 DC HC_SUSPEND signals from USB_SUSPEND 1 0 Setting these bit HIGH disables control of ISP1761 DC HC_SUSPEND and the signals are pulled high on the device 24 23 Read write USB_SUSPEND 1 0 bXX USB_SUSPEND0 controls ISP1761 DC_SUSPEND USB_SUSPEND1 controls ISP1761 HC_SUSPEND See USB interface on page 4 39 for more information about the ISP1761 USB controller ...

Page 58: ...age 4 19 Configurations See Table 4 15 on page 4 19 Attributes See Table 4 3 on page 4 8 Figure 4 11 shows the bit assignments Figure 4 11 SYS_PROCID0 Register bit assignments Undefined 31 0 DMA select 1 2 Table 4 14 SYS_DMA Register bit assignments Bits Name Reset Description 31 2 0x0000 Undefined 1 0 DMA select DMA ACK REQ pair select 00 AACI RX SB_nDRQ nDACK 0 AACI TX SB_nDRQ nDACK 1 01 AACI RX...

Page 59: ...x04 ARM1136 0x06 ARM11MPCore 0x08 ARM1156 0x0A ARM1176 0x0C Cortex A9 0x0E Cortex A8 0x10 Cortex R4 0x12 Cortex A5 0x14 Cortex A15 0x18 Cortex A7 0x16 Cortex R5 0x1A Cortex R7 0xFF CoreTile not supported Also used to indicate a LogicTile Express image 23 20 BOARD_REVISION Depends on daughterboard Returns the board revision Examples are 0x0 A 0x1 B 0x2 C 19 16 BOARD_VARIANT Depends on daughterboard...

Page 60: ...0x00 ARM7TDMI 0x02 ARM9xx 0x04 ARM1136 0x06 ARM11MPCore 0x08 ARM1156 0x0A ARM1176 0x0C Cortex A9 0x0E Cortex A8 0x10 Cortex R4 0x12 Cortex A5 0x14 Cortex A15 0x18 Cortex A7 0x16 Cortex R5 0x1A Cortex R7 0xFF CoreTile not supported Also used to indicate a LogicTile Express image 23 20 BOARD_REVISION Depends on daughterboard Returns the board revision Examples are 0x0 A 0x1 B 0x2 C 19 16 BOARD_VARIA...

Page 61: ... the SYS_CFGCTRL register with the correct function and destination value For example to read from the Motherboard oscillator 1 set the SYS_CFGCTRL register to 0x80100001 Start 1 Write 1 DCC 0 Function 1 OSC Site 0 MB Position 0 Device 1 oscillator 1 Wait for the SYS_CFGSTAT Complete bit to be set to indicate that the read or write transfer has completed For reads you must read the SYS_CFGDATA reg...

Page 62: ...s Attributes See Table 4 3 on page 4 8 Figure 4 13 shows the register bit assignments Figure 4 13 SYS_CFGCTRL Register bit assignments Table 4 18 shows the register bit assignments 31 0 DCC Function Position Device 11 12 15 16 18 19 20 25 26 17 29 30 Site Undefined Write Start Table 4 18 SYS_CFGCTRL Register bit assignments Bits Name Description 31 Start Initiates the transfer 30 Write Read or wri...

Page 63: ...ter bit assignments continued Bits Name Description Table 4 19 SYS_CFGCTRL function values Value Name Format Range Function 1 SYS_CFG_OSC Frequency Hz 1Hz 4 3GHz Oscillator value 2 SYS_CFG_VOLT Voltage µV 1µV 4 3kV Voltage value 3 SYS_CFG_AMP Current µA 1µA 4 3kA Current value 4 SYS_CFG_TEMP Temperature µC 1µC 4 3kC Temperature value 5 SYS_CFG_RESET DB reset register 6 SYS_CFG_SCC 32 bit register ...

Page 64: ...he SYS_CFG registers Example 4 1 Pseudo code for changing the SYS_CFG registers Sys_cfg write function site position dcc device data check if busy if SYS_CFGCTRL SYS_CFG_START return FAILURE clear the complete bit in the SYS_CFGSTAT status register SYS_CFGSTAT 0 if write write data SYS_CFGDATA data set control register SYS_CFGCTRL SYS_CFG_START SYS_CFG_WRITE dcc function site position device wait ...

Page 65: ...tial else set control register SYS_CFGCTRL SYS_CFG_START dcc function site position device wait for complete flag to be set while SYS_CFGSTAT SYS_CFG_COMPLETE check error status flag and return error flag if set if SYS_CFGSTAT SYS_CFG_ERROR return FAILURE else read data data SYS_CFGDATA return SUCCESS ...

Page 66: ...ripheral that is developed tested and licensed by ARM Table 4 21 shows the AACI implementation PrimeCell Modifications The AACI PrimeCell in the motherboard FPGA has a different FIFO depth than the standard PL041 Figure 4 15 on page 4 27 shows the register bit assignments Table 4 21 AACI implementation Property Value Location Motherboard IO FPGA Memory base address ARM Legacy memory map SMB CS7 ba...

Page 67: ... controller This controller is in the IO FPGA and is intended for use with daughterboards that do not contain their own CLCD controller 0 31 7 8 Undefined 5 6 2 3 FIFO depth Number of channels Reserved Table 4 22 Modified AACI PeriphID3 Register bit assignments Bit Access Name Description 31 8 Write as zeros read is undefined Undefined 7 6 Read modify write to preserve value Reserved Reserved 5 3 ...

Page 68: ...n Different display resolutions require different data and synchronization timing Use registers CLCD_TIM0 CLCD_TIM1 CLCD_TIM2 and OSCCLK1 to define the display timings The mapping of the 32 bits of pixel data in memory to the RGB display signals depends on the resolution and the display mode For information on setting the red green and blue brightness for direct non palettized 24 bit and 16 bit co...

Page 69: ...terface CompactFlash Control Register The CF_CTRL Register characteristics are Purpose The CompactFlash control register 0x0001A300 provides control and status information for the inserted CF card If your daughterboard uses the ARM Legacy memory map the CompactFlash control register is at SMB CS7 base address 0x1A000 If your daughterboard uses the ARM Cortex A Series memory map the CompactFlash co...

Page 70: ...3 chip select Note See the Technical Reference Manual for your daughterboard 0 31 Undefined 1 10 9 8 7 CF_nCD1 2 3 Reserved CF_PWR_CONTROL CF_RESETn CFPOWER CF_nCD2 Undefined Pulse 15 16 20 19 Table 4 25 CF_CTRL Register bit assignments Bits Access Name Reset Description 31 20 Write ignored read as zero 0x00000 Undefined 19 16 Read write Pulse 0x00000 Pulse width 15 10 Write ignored read as zero 0...

Page 71: ...que MAC address is displayed on a sticker on the motherboard The default MAC address can be temporarily overwritten by the value in the config txt file See the ARM Versatile Express Configuration Technical Reference Manual Table 4 26 Ethernet implementation Property Value Location Motherboard IO FPGA Memory base address ARM Legacy memory map SMB CS3 base address 0x2000000 ARM Cortex A Series memor...

Page 72: ...rmation about the KMI interface 4 5 6 MultiMedia Card Interface MCI The PL180 PrimeCell Multimedia Card Interface MCI is an AMBA compliant SoC peripheral that is developed tested and licensed by ARM The interface supports both Multimedia Cards and Secure Digital cards The internal registers of the MCI interface are memory mapped onto a static memory bus chip select The chip select that they map on...

Page 73: ...ing for a programmed number of seconds You can mask the interrupt by writing to the interrupt match set or clear register The internal registers of the RTC are memory mapped onto a static memory bus chip select The chip select that they map onto depends on the memory map your daughterboard is using as follows ARM legacy memory map The registers map onto the CS7 chip select Cortex A Series memory m...

Page 74: ...onnector on the rear panel The internal registers of the two wire serial bus interface are memory mapped onto a static memory bus chip select The chip select that they map onto depends on the memory map your daughterboard is using as follows ARM legacy memory map The registers map onto the CS7 chip select Cortex A Series memory map The registers map onto the CS3 chip select Note See the Technical ...

Page 75: ...ress Description PCIe 0xD0 0xD1 PCIe switch configuration DVI external display Display dependant Display dependant The DVI serial bus configures the DVI controller for the current screen resolution The MCC initializes the DVI controller on power up to the value set by the configuration file You can also configure the serial bus to bypass the DVI controller and communicate directly with the video m...

Page 76: ... the Dual Timer module are memory mapped onto a static memory bus chip select The chip select that they map onto depends on the memory map your daughterboard is using as follows ARM legacy memory map The registers map onto the CS7 chip select Cortex A Series memory map The registers map onto the CS3 chip select Note See the Technical Reference Manual for your daughterboard Table 4 33 SBCon 1 seria...

Page 77: ...ghterboard is using as follows ARM legacy memory map The registers map onto the CS7 chip select Cortex A Series memory map The registers map onto the CS3 chip select Note See the Technical Reference Manual for your daughterboard Table 4 34 Timer implementation Property Value Location Motherboard IO FPGA Memory base address ARM Legacy memory map Timer 0 1 SMB CS7 base address 0x11000 Timer 2 3 SMB ...

Page 78: ...rted No independent receive clock Table 4 35 UART implementation Property Value Location Motherboard IO FPGA Memory base address ARM Legacy memory map UART 0 SMB CS7 base address 0x9000 UART 1 SMB CS7 base address 0xA000 UART 2 SMB CS7 base address 0xB000 UART 3 SMB CS7 base address 0xC000 Cortex A Series memory map UART 0 SMB CS3 base address 0x90000 UART 1 SMB CS3 base address 0xA0000 UART 2 SMB...

Page 79: ...device controller The USB host has two downstream ports The OTG can function as either a host or slave device The internal registers of the USB interface are memory mapped onto a static memory bus chip select The chip select that they map onto depends on the memory map your daughterboard is using as follows ARM legacy memory map The registers map onto the CS3 chip select Cortex A Series memory map...

Page 80: ...lure The internal registers of the Watchdog module are memory mapped onto a static memory bus chip select The chip select that they map onto depends on the memory map your daughterboard is using as follows ARM legacy memory map The registers map onto the CS7 chip select Table 4 37 USB controller base address Address Description ARM Legacy memory map SMB CS3 base address 0x03000000 ARM Cortex A Ser...

Page 81: ...n about the Watchdog Note The Watchdog counter is disabled if the core is in debug state Table 4 38 Watchdog implementation Property Value Location Motherboard IO FPGA Memory base address ARM Legacy memory map SMB CS7 base address 0xF000 ARM Cortex A Series memory map SMB CS2 base address 0xF0000 Interrupt 0 DMA Release version ARM WDOG SP805 r2p0 Platform Library support No support provided Refer...

Page 82: ...criptions This appendix provides a summary of signals present on the motherboard connectors It contains the following sections Audio CODEC interface on page A 2 UART interface on page A 3 Note This appendix only covers non standard connectors or non standard signal connections to an industry standard connector ...

Page 83: ...log ground to help prevent noise pickup Figure A 1 shows the pinouts of the sockets Note A link LK1 on the motherboard enables a 5V bias voltage to be applied to the microphone The available link options are Fit A B For BIAS at the tip standard active microphone Fit B C For BIAS at the middle sleeve Omit For no BIAS passive microphone When no plug is inserted both the Microphone and Line In jack s...

Page 84: ...ART1 are used for remote control the interface to the MCC log file output or Boot Monitor interface See Chapter 3 Configuration Table A 1 Serial plug signal assignment Pin UART0 J24A top UART1 J24B bottom UART2 J25A top UART3 J25B bottom 1 SER0_DCD NC NC NC 2 SER0_RX SER1_RX SER2_RX SER3_RX 3 SER0_TX SER1_TX SER2_TX SER3_TX 4 SER0_DTR SER1_DTRa a The SER1_DTR SER2_DTR and SER3_DTR signals are conn...

Page 85: ...ll rights reserved B 1 ID052914 Non Confidential Appendix B Specifications This appendix contains the specification for the motherboard It contains the following sections Timing specifications on page B 2 Electrical Specification on page B 7 ...

Page 86: ...nt the timing requirements in this section B 1 1 SMB synchronous read Figure B 1 shows the synchronous read timing Figure B 1 Synchronous read timing The intervals are Tsmbis 6ns Tsmbov 7 5ns Tsmboh Tperiod 2 Toe_n 1 cycle minimum Trc_ncs7 5 cycles minimum Trc_ncs3 7 cycles minimum All signals are clocked off SMB_CLKO SMB_CLKI is transmitted by the IO FPGA but it does not clock any data SMB_ADDR A...

Page 87: ...write timing The intervals are Tsmbis 6ns Tsmbov 7 5ns Tsmbih 0ns Twp 2 cycles minimum Trc_ncs7 5 cycles minimum Trc_ncs3 7 cycles minimum All signals are clocked off SMB_CLKO SMB_CLKI is transmitted by the IO FPGA but it does not clock any data SMB_ADDR ADDR SMB_CLKO Tsmbis SMB_CLKI RDATA SMB_DATA SMB_nWE SMB_nCS SMB_nWAIT Wait_req_SMB_CLKI Wait_req_SMB_CLKO Trc Twp Tsmbov Tsmbfih Tperiod SMB_nAD...

Page 88: ... of latency All IOFPGA SMB input signals are registered on the rising edge of SMB_CLKO They are then registered a second time before being output to the SMB bus This adds 2 clock cycles of latency An asynchronous read has a penalty of 1 5 clock cycles for the control signals to leave the IO FPGA and an additional 2 clocks for the read data to be passed back The total delay is 3 5 clock cycles B 1 ...

Page 89: ... 1 5 clock cycles of latency All IOFPGA SMB input signals are registered on the rising edge of SMB_CLKO They are then registered a second time before being output to the SMB bus This adds 2 clock cycles of latency An asynchronous write therefore has a penalty of 1 5 clock cycles because of going though the IO FPGA B 1 5 Video multiplexer FPGA timing Figure B 5 on page B 6 shows the video multiplex...

Page 90: ..._MCLK Tis 5 30ns Tih 0 00ns Audio data clocked by MMB_SCLK Tis 2 65ns Tih 0 00ns User LEDS Video SRAM NOR FLASH 0 User SRAM USB Ethernet NOR FLASH 1 Compact Flash 2 x KMI SD MMC AACI 4 x UART MMB Mux Matrix multiplexers and bridges I O FPGA CS0 Peripherals PCIe I2C Motherboard Configuration Controller Interrupts and DMA control DVI CS3 CS4 CS1 CS2 CS2 CS2 CB Site 1 Site 2 Site 1 Site 2 SB_GCLK MMB...

Page 91: ...herboard Although the 3V3 voltage regulator can supply 1A to each stack ARM recommends that each daughterboard draws only 100mA to give each stack a 200mA safety margin These values represent the motherboard PCB tracking and regulator component limits Table B 1 Motherboard electrical characteristics Symbol Description Min Max Peak Unit 12V 12V from ATX power supply 0 10 10 A 5V 5V from ATX power s...

Page 92: ...able C 2 Differences between Issue A and Issue B Change Location Affects Remove USB and LAN from the Note about nCS3 Static Memory Bus on page 2 4 All versions Clarified the location of the SB_GLCK signal Figure 2 4 on page 2 13 All versions Clarified the address offsets for peripherals NOR Flash SRAM Ethernet and USB in the motherboard memory map Table 4 1 on page 4 4 All versions Added descripti...

Page 93: ... 6 on page 3 15 All versions AUTORUN WDTRESET and PCIMASTER added to Example config txt file and CONFIGURATION section below the example Figure 3 6 on page 3 15 All versions Information on image txt file updated with more user information Contents of the directory for CoreTile Express boards on page 3 19 All versions Example Typical motherboard board txt file updated to show additional range infor...

Page 94: ...ATION section Example 3 3 on page 3 16 CONFIGURATION section on page 3 16 All versions Example board txt file for Site 2 with more than one Daughterboard Configuration Controller added Example 3 10 on page 3 24 All versions Note added to Debug menu section Debug menu on page 3 28 All versions Debug commands table updated for more than one Daughterboard Configuration Controller device Table 3 4 on ...

Page 95: ... Real Time Clock RTC on page 4 33 Two wire serial bus interface SBCon on page 4 34 Timers on page 4 36 UART on page 4 37 USB interface on page 4 39 Watchdog on page 4 40 All versions Text references diagrams and new diagrams added to include the new memory map the ARM Cortex A Series memory map Existing references to existing memory map changed to ARM legacy memory map config txt generic motherboa...

Page 96: ...otherboard configuration file on page 3 16 All versions New section added to describe Hardware RESET and Soft reset transitions Push button and remote resets on page 3 9 All versions Debug commands table updated to include PCI read and write commands Other updates made to Debug commands table Table 3 4 on page 3 28 All versions EEPROM commands table updated to include new commands Table 3 5 on pag...

Page 97: ...descriptions SYS_ PROCID0 Register on page 4 18 SYS_PRODCID1 Register on page 4 19 All versions Added energy meter to list of SYS_CFGCTRL function values Table 4 19 on page 4 23 All versions Clarified references to RAM Terms user SRAM or video SRAM used instead of previous terminology Figure 2 1 on page 2 2 Static Memory Bus on page 2 4 Figure 2 4 on page 2 13 Figure 2 5 on page 2 14 Table 4 1 on ...

Page 98: ...f motherboard voltage regulators by CoreTile Express or LogicTile Express daughterboards Table B 2 on page B 7 All versions Table C 10 Differences between Issue I and Issue J Change Location Affects Updated description of PCI Express daughterboard root complex Motherboard supports a root complex on either daughterboard but not both By default the root complex is on the daughterboard in Site 1 The ...

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