Programmers Model
ARM DUI 0447J
Copyright © 2009-2014, ARM. All rights reserved.
4-40
ID052914
Non-Confidential
The ISP1761 has the following features:
•
Includes high-performance USB peripheral controller with integrated Serial Interface
Engine, FIFO memory, and transceiver.
•
Configurable number of downstream and upstream hosts or functions.
•
USB host supports 480Mb/s, 12Mb/s, and 1.5Mb/s.
•
Programmable interrupts and DMA.
•
FIFO and 63KB on-chip RAM for USB.
Table 4-37
shows the ISP1761 register address offsets from the CS3 base address.
4.5.12
Watchdog
The SP805 Watchdog module is an AMBA-compliant SoC peripheral that is developed, tested,
and licensed by ARM.
The Watchdog module consists of a 32-bit down counter with a programmable time-out interval
that has the capability to generate an interrupt and a reset signal on timing out. You can use this
to apply a reset to a system in the event of a software failure.
The internal registers of the Watchdog module are memory-mapped onto a static memory bus
chip select. The chip select that they map onto depends on the memory map your daughterboard
is using as follows:
•
ARM legacy memory map:
—
The registers map onto the CS7 chip select.
Table 4-37 USB controller base address
Address
Description
•
ARM Legacy memory map:
—
SMB CS3 base a
0x03000000
•
ARM
Cortex-A Series
memory map:
—
SMB CS2 base a
0x03000000
Host controller EHCI registers
•
ARM Legacy memory map:
—
SMB CS3 base a
0x03002000
—
SMB CS3 base a
0x03003000
•
ARM
Cortex-A Series
memory map:
—
SMB CS2 base a
0x03002000
—
SMB CS3 base a
0x03003000
Peripheral controller registers
Host controller configuration registers
Peripheral controller registers
Host controller configuration registers
•
ARM Legacy memory map:
—
SMB CS3 base a
0x03000370
•
ARM
Cortex-A Series
memory map:
—
SMB CS2 base a
0x03000370
OTG controller registers
•
ARM Legacy memory map:
—
SMB CS3 base a
0x03000400
•
ARM
Cortex-A Series
memory map:
—
SMB CS2 base a
0x03000400
Host controller buffer memory, 63KB
