Hardware Description
ARM DUI 0447J
Copyright © 2009-2014, ARM. All rights reserved.
2-20
ID052914
Non-Confidential
2.7
DMA signals
The motherboard does not contain a
DMA Controller
(DMAC). However, it does enable routing
of two DMA
ACK
/
REQ
handshake signal pairs from selected IO FPGA peripherals to CoreTile
Express or LogicTile Express daughterboards. These daughterboards might contain a DMAC.
See your daughterboard documentation or application note for more information.
There are eight DMA handshake signal pairs that run between the daughterboard tile sites
through the System Bus. Six of these pairs,
SB_nDRQ[7:2]
and
SB_nDACK[7:2]
, have no
connection to the motherboard IO FPGA. You can use a DMAC in one daughterboard site to
communicate with peripherals in the other daughterboard site. Two of the eight pairs,
SB_nDRQ[1:0]
and
SB_nDACK[1:0]
, also connect to the motherboard IO FPGA. These are
only used for handshaking between the two selected peripherals in the IO FPGA and a DMAC
in one of the daughterboard sites. See
Figure 2-9
.
The motherboard IO FPGA implements a DMA router that selects two DMAC-capable
motherboard peripherals for connection to the DMAC pins on one of the daughterboard sites.
You must ensure that only one daughterboard makes active connections to these signals.
You can route the following combinations of motherboard peripherals to a daughterboard site
DMAC:
•
AACI RX + AACI TX
•
AACI RX + MCI
•
AACI TX + MCI
•
UART0 RX + UART0 TX.
See
DMA Channel Selection Register
on page 4-17
for the routers SYS_DMA register bit
definitions.
Figure 2-9 DMA architecture
Motherboard Express μATX
LogicTile Express daughterboard
(in Site 2)
CoreTile Express daughterboard
(in Site 1)
HDRY
Test chip
FPGA
HDRY1
HDRY2
IO FPGA
SB2
SB1
6
6
2
2
SB_nDRQ[7:2]
SB_nDACK[7:2]
SB_nDRQ[1:0]
SB_nDACK[1:0]
SB_nDACK[1:0]
SB_nDRQ[1:0]
HDRY
SB_nDRQ[7:2]
SB_nDACK[7:2]
SB_nDRQ[1:0]
SB_nDACK[1:0]
