Hardware Description
ARM DUI 0447J
Copyright © 2009-2014, ARM. All rights reserved.
2-16
ID052914
Non-Confidential
These are connected through a IDT89PES32H8 PCI Express switch to the PCIe buses from the
two daughterboards.
You can configure the PCIe switch to work with CoreTile Express or LogicTile Express
daughterboards configured as an integrated PCI-Express root complex.
Note
The V2M-P1 motherboard supports a
root complex
either on the daughterboard in Site 1 or on
the daughterboard in Site 2. You select which site contains the
root complex
by editing the
config.txt
file. By default, the daughterboard in Site 1 is the root complex.
The V2M-P1 motherboard does not support an
endpoint
either on the daughterboard in Site 1
or the daughterboard in Site 2.
The PCIe slots are the only endpoints and conform to the PCI-Express 1.0 specification. There
is no PCIe endpoint in the motherboard IO FPGA. Because there are no PCIe lanes connected
to the motherboard, peripherals in the IO FPGA cannot be accessed from the PCIe bus.
The MCC on the motherboard controls the following PCIe features:
•
Configuring PCIe eeprom settings.
•
RESETS to each connector and daughterboard.
The IO FPGA provides the I2C bus to the PCIe switch.
Figure 2-7 on page 2-17
shows the PCIe block diagram. See also
Clock architecture
on
page 2-9
.
