Programmers Model
ARM DUI 0447J
Copyright © 2009-2014, ARM. All rights reserved.
4-35
ID052914
Non-Confidential
Table 4-30
provides information about the serial bus interface.
Table 4-31
shows the registered device addresses.
Table 4-32
shows the registers that control the serial bus interface.
Table 4-30 Serial bus implementation
Property
Value
Location
Motherboard IO FPGA
Memory base address
•
ARM Legacy memory map:
—
SMB CS7 base a
0x2000
- PCIe.
—
SMB CS7 base a
0x16000
- DVI.
•
Cortex-A Series
memory map:
—
SMB CS3 base a
0x30000
- PCIe.
—
SMB CS3 base a
0x16000
- DVI.
Interrupt
-
DMA
-
Release version
Custom logic
Reference documentation
VESA DDC Specification Version 3.0
Table 4-31 Serial interface device addresses
Device
Write address
Read address
Description
PCIe
0xD0
0xD1
PCIe switch configuration
DVI, external display
Display dependant
Display dependant
The DVI serial bus configures the DVI controller for the current
screen resolution. The MCC initializes the DVI controller on
power-up to the value set by the configuration file. You can also
configure the serial bus to bypass the DVI controller and
communicate directly with the video monitor to determine the
monitor type.
Table 4-32 SBCon 0 serial bus register
Address
Name
Access
Description
•
ARM Legacy memory map:
—
CS7 +
0x00002000
•
Cortex-A Series
memory map:
—
C3 +
0x00002000
SB_CONTROL
Read
Read serial control bits:
Bit [0] is
SCL
Bit [1] is
SDA
•
ARM Legacy memory map:
—
CS7 +
0x00002000
•
Cortex-A Series
memory map:
—
CS3 +
0x00002000
SB_CONTROLS
Write
Set serial control bits:
Bit [0] is
SCL
Bit [1] is
SDA
•
ARM Legacy memory map:
—
CS7 +
0x00002004
•
Cortex-A Series
memory map:
—
CS3 +
0x00002004
SB_CONTROLC
Write
Clear serial control bits:
Bit [0] is
SCL
Bit [1] is
SDA