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Level 1 Memory System

ARM DDI 0388I

Copyright © 2008-2012 ARM. All rights reserved.

7-8

ID073015

Non-Confidential

7.4

About the L1 data side memory system

The L1 data cache is organized as a physically indexed and physically tagged cache. The micro
TLB produces the physical address from the virtual address before performing the cache access.

7.4.1

Local Monitor

The L1 memory system of the Cortex-A9 processor has a local monitor. This is a 2-state, open
and exclusive, state machine that manages load/store exclusive (

LDREXB

,

LDREXH

,

LDREX

,

LDREXD

,

STREXB

,

STREXH

,

STREX

and

STREXD

) accesses and clear exclusive (

CLREX

) instructions. You can use

these instructions to construct semaphores, ensuring synchronization between different
processes running on the processor, and also between different processors that are using the
same coherent memory locations for the semaphore.

Note

A store exclusive can generate an MMU fault or cause the processor to take a data watchpoint
exception regardless of the state of the local monitor. See

Table 10-8 on page 10-11

.

See the

ARM Architecture Reference Manual

for more information about these instructions.

Treatment of intervening STR operations

In cases where there is an intervening

STR

operation in an

LDREX

/

STREX

code sequence, the

intermediate

STR

does not produce any effect on the internal exclusive monitor. The local

monitor is in the Exclusive Access state after the

LDREX

, remains in the Exclusive Access state

after the

STR

, and returns to the Open Access state only after the

STREX

.

LDREX/STREX operations using different sizes

In cases where the LDREX and STREX operations are of different sizes a check is performed
to ensure that the tagged address bytes match or are within the size range of the store operation.

The granularity of the tagged address for an

LDREX

instruction is eight words, aligned on an

8-word boundary. This size is implementation-defined, and as such, software must not rely on
this granularity remaining constant on other ARM cores.

7.4.2

External aborts handling

The L1 data cache handles two types of external abort depending on the attributes of the
memory region of the access:

•

All Strongly-ordered accesses use the synchronous abort mechanism.

•

All Cacheable, Device, and Normal Non-cacheable memory requests use the
asynchronous abort mechanism. For example, an abort returned on a read miss, issuing a
linefill, is flagged as asynchronous.

7.4.3

Cortex-A9 behavior for Normal Memory Cacheable memory regions

Depending on its configuration settings, and on the inner attributes specified in the page table
descriptors, the Cortex-A9 cacheable accesses behave as follows:

SCTLR.C=0

The Cortex-A9 L1 Data Cache is not enabled. All memory accesses to Normal
Memory Cacheable regions are treated as Normal Memory Non-Cacheable,
without lookup and without allocation in the L1 Data Cache.

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Summary of Contents for Cortex A9

Page 1: ...Copyright 2008 2012 ARM All rights reserved ARM DDI 0388I ID073015 Cortex A9 Revision r4p1 Technical Reference Manual ...

Page 2: ... to assist the reader in the use of the product ARM shall not be liable for any loss or damage arising from the use of any information in this document or any error or omission in such information or any incorrect use of the product Where the term ARM is used it means ARM or any of its subsidiaries as appropriate Confidentiality Status This document is Non Confidential The right to use copy and di...

Page 3: ...gurable options 1 8 1 7 Test features 1 9 1 8 Product documentation and design flow 1 10 1 9 Product revisions 1 12 Chapter 2 Functional Description 2 1 About the functions 2 2 2 2 Interfaces 2 4 2 3 Clocking and resets 2 6 2 4 Power management 2 10 2 5 Constraints and limitations of use 2 15 Chapter 3 Programmers Model 3 1 About the programmers model 3 2 3 2 ThumbEE architecture 3 3 3 3 The Jazel...

Page 4: ...n side memory system 7 5 7 4 About the L1 data side memory system 7 8 7 5 About DSB 7 10 7 6 Data prefetching 7 11 7 7 Parity error support 7 12 Chapter 8 Level 2 Memory Interface 8 1 About the Cortex A9 L2 interface 8 2 8 2 Optimized accesses to the L2 memory interface 8 7 8 3 STRT instructions 8 9 Chapter 9 Preload Engine 9 1 About the Preload Engine 9 2 9 2 PLE control register descriptions 9 3...

Page 5: ...onitoring signals A 14 A 9 Exception flags signal A 17 A 10 Parity signal A 18 A 11 MBIST interface A 19 A 12 Scan test signal A 20 A 13 External Debug interface A 21 A 14 PTM interface signals A 24 Appendix B Cycle Timings and Interlock Behavior B 1 About instruction cycle timing B 2 B 2 Data processing instructions B 3 B 3 Load and store instructions B 4 B 4 Multiplication instructions B 7 B 5 B...

Page 6: ...t 2008 2012 ARM All rights reserved vi ID073015 Non Confidential Preface This preface introduces the Cortex A9 Technical Reference Manual TRM It contains the following sections About this book on page vii Feedback on page xi ...

Page 7: ...CU See the Cortex A9 MPCore Technical Reference Manual for a description Using this book This book is organized into the following chapters Chapter 1 Introduction Read this for an introduction to the Cortex A9 processor and its features Chapter 2 Functional Description Read this for a description of the functionality of the Cortex A9 processor Chapter 3 Programmers Model Read this for a descriptio...

Page 8: ...ary The ARM Glossary is a list of terms used in ARM documentation together with definitions for those terms The ARM Glossary does not contain terms that are industry standard unless the ARM meaning differs from the generally accepted meaning See ARM Glossary http infocenter arm com help topic com arm doc aeg0014 index html Conventions This book uses the conventions that are described in Typographi...

Page 9: ... within the shaded area at that time The actual level is unimportant and does not affect normal operation Key to timing diagram conventions Timing diagrams sometimes show single bit signals as HIGH and LOW at the same time and they look similar to the bus change shown in Key to timing diagram conventions If a timing diagram shows a single bit signal in this way then its value does not affect the a...

Page 10: ...ght PTM A9 Technical Reference Manual ARM DDI 0401 CoreSight PTM A9 Integration Manual ARM DII 0162 CoreSight Program Flow Trace Architecture Specification v1 0 ARM IHI 0035 CoreLink Level 2 Cache Controller L2C 310 Technical Reference Manual ARM DDI 0246 AMBA AXI Protocol Specification ARM IHI 0022 ARM Generic Interrupt Controller Architecture Specification ARM IHI 0048 PrimeCell Generic Interrup...

Page 11: ...ith as much information as you can provide Include symptoms and diagnostic procedures if appropriate Feedback on content If you have comments on content then send an e mail to errata arm com Give the title the number ARM DDI 0388I the page numbers to which your comments apply a concise explanation of your comments ARM also welcomes general suggestions for additions and improvements Note ARM tests ...

Page 12: ... A9 processor and its features It contains the following sections About the Cortex A9 processor on page 1 2 Cortex A9 variants on page 1 4 Compliance on page 1 5 Features on page 1 6 Interfaces on page 1 7 Configurable options on page 1 8 Test features on page 1 9 Product documentation and design flow on page 1 10 Product revisions on page 1 12 ...

Page 13: ...n to the ARMv7 A architecture It provides support for integer and floating point vector operations NEON MPE can accelerate the performance of multimedia applications such as 3 D graphics and image processing When implemented the NEON MPE option extends the processor functionality to provide support for the ARMv7 Advanced SIMD and VFPv3 D 32 instruction sets See the Cortex A9 NEON Media Processing ...

Page 14: ...imeCell Generic Interrupt Controller PL390 can be attached to the Cortex A9 uniprocessor The Cortex A9 MPCore contains an integrated interrupt controller that shares the same programmers model as the PL390 although there are implementation specific differences See the Cortex A9 MPCore Technical Reference Manual for a description of the Cortex A9 MPCore Interrupt Controller CoreLink Level 2 Cache C...

Page 15: ...tions on Cortex A9 MPCore AXI master interfaces Cortex A9 uniprocessor accesses to private memory regions an Interrupt Controller IC with support for legacy ARM interrupts a private timer and a private watchdog per processor a global timer AXI high speed Advanced Microprocessor Bus Architecture version 3 AMBA 3 L2 interfaces an Accelerator Coherency Port ACP that is an optional AXI 64 bit slave po...

Page 16: ...loating Point version 3 VFPv3 architecture extension for floating point computation that is fully compliant with the IEEE 754 standard Security Extensions for enhanced security Multiprocessing Extensions for multiprocessing functionality See the ARM Architecture Reference Manual ARMv7 A and ARMv7 R edition 1 3 2 Advanced Microcontroller Bus Architecture The Cortex A9 processor complies with the AM...

Page 17: ...chitecture v7 A instruction set Security Extensions Harvard level 1 memory system with Memory Management Unit MMU two 64 bit AXI master interfaces with Master 0 for the data side bus and Master 1 for the instruction side bus ARMv7 Debug architecture support for trace with the Program Trace Macrocell PTM interface support for advanced power management with up to three power domains optional Preload...

Page 18: ...e processor has the following external interfaces AMBA AXI interfaces Debug v7 compliant interface including a debug APBv3 external debug interface DFT For more information on these interfaces see AMBA AXI Protocol Specification CoreSight Architecture Specification Cortex A9 MBIST Controller Technical Reference Manual ...

Page 19: ...scriptors 1024 2048 4096 8192 or 16384 descriptors Instruction micro TLB 32 or 64 entries Jazelle Architecture Extension Full or trivial Media Processing Engine with NEON technology Included or nota a The MPE and FPU RTL options are mutually exclusive If you choose the MPE option the MPE is included along with its VFPv3 D32 FPU and the FPU RTL option is not available in this case When the MPE RTL ...

Page 20: ...73015 Non Confidential 1 7 Test features The Cortex A9 processor provides test signals that enable the use of both ATPG and MBIST to test the Cortex A9 processor and its memory arrays See Appendix A Signal Descriptions and the Cortex A9 MBIST Controller Technical Reference Manual ...

Page 21: ... the multiprocessor variant of the Cortex A9 processor the Cortex A9 Floating Point Unit FPU TRM describes the implementation specific FPU parts of the data engine the Cortex A9 NEON Media Processing Engine TRM describes the Advanced SIMD Cortex A9 implementation specific parts of the data engine If you are programming the Cortex A9 processor then contact the implementer to determine the build con...

Page 22: ...tex A9 processor The operation of the final device depends on Build configuration The implementer chooses the options that affect how the RTL source files are pre processed These options usually include or exclude logic that affects one or more of the area maximum frequency and features of the resulting macrocell Configuration inputs The integrator configures some features of the Cortex A9 process...

Page 23: ...uences r1p0 includes dynamic high level clock gating of the Cortex A9 processor See Dynamic high level clock gating on page 2 8 MAXCLKLATENCY 2 0 bus added See Configuration signals on page A 5 Addition of CP15 power control register See Power Control Register on page 4 41 Extension of the Performance Monitoring Event bus In r1p0 PMUEVENT is 52 bits wide Addition of Cortex A9 specific events See T...

Page 24: ... 6 on page 11 8 and Table A 18 on page A 14 Change to voltage domains See Figure 2 4 on page 2 14 NEON Busy Register See NEON Busy Register on page 4 42 ID Register values changed to reflect correct revision r2p0 r2p1 No functional changes r2p1 r2p2 No functional changes Documentation updates and corrections only See Differences between issue D and issue F on page C 6 r2p2 r3p0 Addition of the REV...

Page 25: ... Chapter 2 Functional Description This chapter describes the functionality of the product It contains the following sections About the functions on page 2 2 Interfaces on page 2 4 Clocking and resets on page 2 6 Power management on page 2 10 Constraints and limitations of use on page 2 15 ...

Page 26: ...ck See About the L1 instruction side memory system on page 7 5 2 1 3 Register renaming The register renaming scheme facilitates out of order execution in Write after Write WAW and Write after Read WAR situations for the general purpose registers and the flag bits of the Current Program Status Register CPSR Dual instruction decode stage Instructions Predictions Instruction prefetch stage Instructio...

Page 27: ...APB Debug interface See Chapter 11 Performance Monitoring Unit 2 1 6 Virtualization of interrupts With virtualized interrupts a guest Operating System OS can use a modified version of the exception behavior model to handle interrupts more efficiently than is possible with a software only solution See Virtualization Control Register on page 4 34 The behavior of the Virtualization Control Register d...

Page 28: ...ypoints are changes in the program flow or events such as branches or changes in context ID that must be output to enable the trace See the CoreSight PTM A9 Technical Reference Manual for more information about tracing with waypoints Program Trace Macrocell PTM is a macrocell that implements the PFT architecture Figure 2 2 shows the PTM interface signals Figure 2 2 PTM interface signals See Append...

Page 29: ...M DDI 0388I Copyright 2008 2012 ARM All rights reserved 2 5 ID073015 Non Confidential Note Only entry to and exit from Jazelle state are traced A waypoint to enter Jazelle state is followed by a waypoint to exit Jazelle state ...

Page 30: ...ng example with ACKLENM0 used with a 3 1 clock ratio between CLK and ACLK in a Cortex A9 uniprocessor Figure 2 3 ACLKENM0 used with a 3 1 clock ratio The master port Master0 changes the AXI outputs only on the CLK rising edge when ACLKENM0 is HIGH 2 3 2 Reset The Cortex A9 processor has the following reset inputs nCPURESET The nCPURESET signal is the main Cortex A9 processor reset It initializes t...

Page 31: ... cycles than this and maximum redundancy can be achieved by applying 15 cycles on every clock domain 3 Stop the CLK clock input to the Cortex A9 uniprocessor If there is a data engine present use NEONCLKOFF See Configuration signals on page A 5 4 Wait for the equivalent of approximately 10 cycles depending on your implementation This compensates for clock and reset tree latencies 5 Release all res...

Page 32: ...g 15 cycles on every clock domain 3 Assert NEONCLKOFF with a value of 1 b1 4 Wait for the equivalent of approximately 10 cycles depending on your implementation This compensates for clock and reset tree latencies 5 Release nNEONRESET 6 Wait for the equivalent of another approximately 10 cycles again to compensate for clock and reset tree latencies 7 Deassert NEONCLKOFF This ensures that all regist...

Page 33: ...d the clock of the integer core is cut in the following cases the integer core is empty and there is an instruction miss causing a linefill the integer core is empty and there is an instruction TLB miss the integer core is full and there is a data miss causing a linefill the integer core is full and data stores are stalled because the linefill buffers are busy When dynamic clock gating is enabled ...

Page 34: ...ses to the tag RAMs and to unnecessary accesses to data RAMs instruction loops that are smaller than 64 bytes often complete without additional instruction cache accesses so lowering power consumption 2 4 2 Cortex A9 processor power control Place holders for level shifters and clamps are inserted around the Cortex A9 processor to ease the implementation of different power domains The Cortex A9 pro...

Page 35: ...e is performed by executing the WFE instruction The transition from the WFE Standby mode to the Run mode is caused by An IRQ interrupt unless masked by the CPSR I bit An FIQ interrupt unless masked by the CPSR F bit An asynchronous abort unless masked by the CPSR A bit A debug event if invasive debug is enabled and the debug event is permitted The assertion of the EVENTI input signal The execution...

Page 36: ...completed The Cortex A9 processor then communicates with the power controller using the STANDBYWFI to indicate that it is ready to enter dormant mode by performing a WFI instruction See Communication to the power management controller on page 2 13 for more information Before removing the power the reset signals to the Cortex A9 processor must be asserted by the external power control mechanism The...

Page 37: ...These signals are only meaningful if the Cortex A9 processor implements power domain clamps See Power management signals on page A 7 DBGNOPWRDWN DBGNOPWRDWN is connected to the system power controller and is interpreted as a request to operate in emulate mode In this mode the Cortex A9 processor and PTM are not actually powered down when requested by software or hardware handshakes See Miscellaneo...

Page 38: ...r clock There is static and dynamic high level clock gating NEON SIMD data paths and logic are in a separate power domain with dedicated clock and reset signals There is static and dynamic high level clock gating When NEON is present you can run FPU non SIMD code without powering the SIMD part or clocking the SIMD part Core0 NEON SIMD CPU0 logic FPU Shared FPU MPE logic and register file Clamp Vmp...

Page 39: ... and limitations of use This section describes memory consistency Memory coherency in a Cortex A9 processor is maintained following a weakly ordered memory consistency model Note When the Shareable attribute is applied to a memory region that is not Write Back Normal memory data held in this region is treated as Non cacheable ...

Page 40: ...ing the processor It contains the following sections About the programmers model on page 3 2 ThumbEE architecture on page 3 3 The Jazelle Extension on page 3 4 Advanced SIMD architecture on page 3 5 Security Extensions architecture on page 3 6 Multiprocessing Extensions on page 3 7 Modes of operation and execution on page 3 8 Memory model on page 3 9 Addresses in the Cortex A9 processor on page 3 ...

Page 41: ...008 2012 ARM All rights reserved 3 2 ID073015 Non Confidential 3 1 About the programmers model The Cortex A9 processor implements the ARMv7 A architecture See the ARM Architecture Reference Manual for information about the ARMv7 A architecture ...

Page 42: ...ved 3 3 ID073015 Non Confidential 3 2 ThumbEE architecture The Thumb Execution Environment ThumbEE extension is a variant of the Thumb instruction set that is designed as a target for dynamically generated code See the ARM Architecture Reference Manual for more information ...

Page 43: ...3 3 The Jazelle Extension The Cortex A9 processor provides hardware support for the Jazelle Extension The processor accelerates the execution of most bytecodes Some bytecodes are executed by software routines See the ARM Architecture Reference Manual for more information See Chapter 5 Jazelle DBX registers ...

Page 44: ...eech processing Note The Advanced SIMD architecture extension its associated implementations and supporting software are commonly referred to as NEON MPE NEON MPE includes both Advanced SIMD instructions and the ARM VFPv3 instructions All Advanced SIMD instructions and VFP instructions are available in both ARM and Thumb states See the ARM Architecture Reference Manual for more information See the...

Page 45: ...usted software such as a complex operating system executes in Non secure state and the more trusted software executes in the Secure state The following sequence is expected to be typical use of the Security Extensions 1 Exit from reset in Secure state 2 Configure the security state of memory and peripherals Some memory and peripherals are accessible only to the software running in Secure state 3 I...

Page 46: ...2012 ARM All rights reserved 3 7 ID073015 Non Confidential 3 6 Multiprocessing Extensions The Multiprocessing Extensions are a set of features that enhance multiprocessing functionality See the ARM Architecture Reference Manual for more information ...

Page 47: ... executes variable length byte aligned Jazelle instructions ThumbEE state The processor executes a variant of the Thumb instruction set designed as a target for dynamically generated code This is code compiled on the device either shortly before or during execution from a portable bytecode or other intermediate or native representation The J bit and the T bit determine the instruction set used by ...

Page 48: ...ory as a linear collection of bytes numbered in ascending order from zero For example bytes 0 3 hold the first stored word and bytes 4 7 hold the second stored word The processor can store words in memory in either big endian format or little endian format Instructions are always treated as little endian Note ARMv7 does not support the BE 32 memory model ...

Page 49: ...instruction cache is indexed by the lower bits of the VA The TLB performs the translation in parallel with the cache lookup The translation uses Secure descriptors if the processor is in the Secure state Otherwise it uses the Non secure descriptors 3 If the protection check carried out by the TLB on the VA does not abort and the PA tag is in the instruction cache the instruction data is returned t...

Page 50: ... Non Confidential Chapter 4 System Control This chapter describes the system control registers their structure operation and how to use them It contains the following sections About system control on page 4 2 Register summary on page 4 3 Register descriptions on page 4 18 ...

Page 51: ...rall system control and configuration MMU configuration and management cache configuration and management system performance monitoring 4 1 1 Deprecated registers In ARMv7 A the following have instruction set equivalents Instruction Synchronization Barrier Data Synchronization Barrier Data Memory Barrier Wait for Interrupt The use of the registers is optional and deprecated In addition the Fast Co...

Page 52: ...c9 registers on page 4 9 c10 registers on page 4 10 c11 registers on page 4 10 c12 registers on page 4 10 c13 registers on page 4 11 c14 registers on page 4 11 c15 registers on page 4 11 All system control coprocessor registers are 32 bits wide except for the Program New Channel operation described in PLE Program New Channel operation on page 9 5 Reserved registers are RAZ WI In addition to listin...

Page 53: ...e 4 1 Column headings definition for CP15 register summary tables Column name Description CRn Register number within the system control coprocessor Op1 Opcode_1 value for the register CRm Operational register number within CRn Op2 Opcode_2 value for the register Name Short form architectural operation or code name for the register Reset Reset value of register Description Cross reference to regist...

Page 54: ...ature Register 0 3 ID_AFR0 RO 0x00000000 Auxiliary Feature Register 0 4 ID_MMFR0 RO 0x00100103 Memory Model Feature Register 0 5 ID_MMFR1 RO 0x20000000 Memory Model Feature Register 1 6 ID_MMFR2 RO 0x01230000 Memory Model Feature Register 2 7 ID_MMFR3 RO 0x00102111 Memory Model Feature Register 3 c2 0 ID_ISAR0 RO 0x00101111 Instruction Set Attributes Register 0 1 ID_ISAR1 RO 0x13112111 Instruction...

Page 55: ...tualization Control Register on page 4 34 a Depends on input signals See System Control Register on page 4 25 b RO in Non secure state if NSACR 18 0 and RW if NSACR 18 1 c The reset value depends on the VFP and NEON configuration If VFP and NEON are implemented and NEON is powered up the reset value is 0x00000000 If VFP is implemented and NEON is not implemented or powered down the reset value is ...

Page 56: ...sters Table 4 7 shows the CP15 system control registers you can access when CRn is c6 Table 4 6 c5 register summary Op1 CRm Op2 Name Type Reset Description 0 c0 0 DFSR RW Data Fault Status Register 1 IFSR RW Instruction Fault Status Register c1 0 ADFSR Auxiliary Data Fault Status Register 1 AIFSR Auxiliary Instruction Fault Status Register Table 4 7 c6 register summary Op1 CRm Op2 Name Type Reset ...

Page 57: ...ruction See Deprecated registers on page 4 2 WO c1 0 ICIALLUIS WO Cache operations registers 6 BPIALLIS WO 7 Reserved WO c4 0 PAR RW c5 0 ICIALLU WO Cache operations registers 1 ICIMVAU WO 2 3 Reserved WO 4 ISB WO User Deprecated registers on page 4 2 6 BPIALL WO Cache operations registers c6 1 DCIMVAC WO 2 DCISW WO 0 c8 0 7 V2PCWPR WO VA to PA operations c10 1 DCCVAC WO Cache operations registers...

Page 58: ...s WO 2 TLBIASIDISb WO 3 TLBIMVAAISa WO c5 c6 or c7 0 TLBIALLa WO 1 TLBIMVAb WO 2 TLBIASIDb WO 3 TLBIMVAAa WO Table 4 10 c9 register summary Op1 CRm Op2 Name Type Reset Description 0 c12 0 PMCR RW 0x41093000 Performance Monitor Control Register 1 PMCNTENSET RW 0x00000000 Count Enable Set Register 2 PMCNTENCLR RW 0x00000000 Count Enable Clear Register 3 PMOVSR RW Overflow Flag Status Register 4 PMSW...

Page 59: ...RRR 13 12 is not implemented RAZ WI c NMRR 29 28 and NMRR 13 12 are not implemented RAZ WI Table 4 12 c11 register summary Op1 CRm Op2 Name Type Reset Description 0 c0 0 PLEIDR ROa PLE ID Register on page 4 36 2 PLEASR ROa PLE Activity Status Register on page 4 36 4 PLEFSR ROa PLE FIFO Status Register on page 4 37 c1 0 PLEUAR Privileged R W User RO Preload Engine User Accessibility Register on pag...

Page 60: ...on 0 c0 0 Power Control Register RWa b Power Control Register on page 4 41 c1 0 NEON Busy Register RO 0x00000000 NEON Busy Register on page 4 42 4 c0 0 Configuration Base Address ROc d Configuration Base Address Register on page 4 42 5 c4 2 Select Lockdown TLB Entry for read WOe TLB lockdown operations on page 4 43 4 Select Lockdown TLB Entry for write WOe c5 2 Main TLB VA register RWe c6 2 Main T...

Page 61: ...ion ID register on page 4 21 c1 0 ID_PFR0 RO 0x00001231 Processor Feature Register 0 1 ID_PFR1 RO 0x00000011 Processor Feature Register 1 2 ID_DFR0 RO 0x00010444 Debug Feature Register 0 3 ID_AFR0 RO 0x00000000 Auxiliary Feature Register 0 4 ID_MMFR0 RO 0x00100103 Memory Model Feature Register 0 5 ID_MMFR1 RO 0x20000000 Memory Model Feature Register 1 6 ID_MMFR2 RO 0x01230000 Memory Model Feature ...

Page 62: ...ntrol Register c3 0 c0 0 DACR RW Domain Access Control Register c10 0 c2 0 PRRRc RW 0x00098AA4 Primary Region Remap Register 1 NMRRd RW 0x44E048E0 Normal Memory Remap Register c13 0 c0 1 CONTEXTIDR RW Context ID Register a Depends on input signals See System Control Register on page 4 25 b In Secure state only You must program the Non secure version with the required value c PRRR 13 12 is not impl...

Page 63: ...depends on the VFP and NEON configuration If VFP and NEON are implemented and NEON is powered up the reset value is 0x00000000 If VFP is implemented and NEON is not implemented or powered down the reset value is 0x80000000 If VFP and NEON are not implemented the reset value is 0xC0000000 Table 4 20 Cache and branch predictor maintenance operations CRn Op1 CRm Op2 Name Type Reset Description c7 0 c...

Page 64: ...med by the WFI instruction See Deprecated registers on page 4 2 b RO in User mode Table 4 23 Performance monitor registers CRn Op1 CRm Op2 Name Type Reset Description c9 0 c12 0 PMCR RW 0x41093000 Performance Monitor Control Register 1 PMCNTENSET RW 0x00000000 Count Enable Set Register 2 PMCNTENCLR RW 0x00000000 Count Enable Clear Register 3 PMOVSR RW Overflow Flag Status Register 4 PMSWINC WO Sof...

Page 65: ...nitor Vector Base Address Register c1 0 ISR RO 0x00000000 Interrupt Status Register a No access in Non secure state b SCR 6 is not implemented RAZ WI c This is RW in Secure state and RO in the Non secure state d 0x00000000 if NEON present and 0x0000C000 if NEON not present e Only the secure version is reset to 0 The Non secure version must be programmed by software Table 4 25 Preload engine regist...

Page 66: ...perations on page 4 43 4 Select Lockdown TLB Entry for write WOd c5 2 Main TLB VA register RWd c6 2 Main TLB PA register RWd c7 2 Main TLB Attribute register RWd a Has no effect on entries that are locked down b Invalidates the locked entry when it matches c No access in Non secure state if NSCAR TL 0 and RW if NSACR TL 1 d No access in Non secure state Table 4 27 Implementation defined registers ...

Page 67: ... MIDR bit assignments Figure 4 1 MIDR bit assignments Table 4 28 shows the MIDR bit assignments To access the MIDR read the CP15 register with MRC p15 0 Rt c0 c0 0 Read Main ID Register Variant Implementer 31 23 20 19 16 15 4 3 0 Architecture Primary part number Revision 24 Table 4 28 MIDR bit assignments Bits Name Function 31 24 Implementer Indicates the implementer code 0x41 ARM Limited 23 20 Va...

Page 68: ...th MRC p15 0 Rd c0 c0 3 returns TLB details 4 3 3 Multiprocessor Affinity Register The MPIDR characteristics are Purpose To identify whether the processor is part of a Cortex A9 MPCore implementation 31 24 23 16 15 8 7 3 2 1 0 SBZ UNP DLSize ILSize SBZ TLB_size nU Table 4 29 TLBTR bit assignments Bits Name Function 31 24 SBZ 23 16 ILsize Specifies the number of instruction TLB lockable entries For...

Page 69: ...o access the MPIDR read the CP15 register with MRC p15 0 Rd c0 c0 5 read Multiprocessor ID register 31 8 7 0 U SBZ SBZ 12 11 Cluster ID 1 2 CPU ID 1 30 29 Table 4 30 MPIDR bit assignments Bits Name Function 31 Indicates the register uses the new multiprocessor format This is always 1 30 U bit Multiprocessing Extensions 0 Processor is part of an MPCore cluster 1 Processor is a uniprocessor 29 12 SB...

Page 70: ...R bit assignments Table 4 31 shows the REVIDR bit assignments To access the REVIDR read the CP15 register with MRC p15 0 Rt c0 c0 6 Read Revision ID Register 4 3 5 Cache Size Identification Register The CCSIDR characteristics are Purpose Provides information about the architecture of the caches selected by CSSELR Usage constraints The CCSIDR is only accessible in privileged modes common to the Sec...

Page 71: ... 29 28 27 13 12 2 0 NumSets Associativity WT WB RA WA Table 4 32 CCSIDR bit assignments Bits Name Function 31 WT Indicates support available for Write Through 0 Write Through support not available 1 Write Through support available 30 WB Indicates support available for Write Back 0 Write Back support not available 1 Write Back support available 29 RA Indicates support available for Read Allocation ...

Page 72: ...CLIDR 4 3 7 Auxiliary ID Register The AIDR characteristics are Purpose Provides implementation specific information Usage constraints The AIDR is only accessible in privileged modes common to the Secure and Non secure states L oUIS CL 7 CL 6 CL 5 CL 4 CL 3 CL 2 CL 1 Reserved 31 30 29 27 26 24 23 21 20 18 17 15 14 12 11 10 8 6 5 3 2 0 LoU LoC Table 4 33 CLIDR bit assignments Bits Name Function 31 3...

Page 73: ...onstraints The CSSELR is only accessible in privileged modes banked for Secure and Non secure states Configurations Available in all configurations Attributes See the register summary in Table 4 2 on page 4 5 Figure 4 7 shows the CSSELR bit assignments Figure 4 7 CSSELR bit assignments Table 4 34 shows the CSSELR bit assignments To access the CSSELR read the CP15 register with MRC p15 2 Rd c0 c0 0...

Page 74: ...gnments Table 4 35 shows the SCTLR bit assignments 31 30 29 28 27 26 25 24 14 13 12 11 10 3 2 1 0 M I NMFI Reserved Reserved Reserved V Z C A 23 22 21 20 19 9 SW bit 18 17 16 15 RR bit TE AFE TRE EE HA Table 4 35 SCTLR bit assignments Bits Name Access Function 31 SBZ 30 TE Banked Thumb exception enable 0 Exceptions including reset are handled in ARM state 1 Exceptions including reset are handled i...

Page 75: ...and RO in Non secure state 0 Random replacement This is the reset value 1 Round robin replacement 13 V Banked Vectors bit This bit selects the base address of the exception vectors 0 Normal exception vectors base address 0x00000000 The Security Extensions are implemented so this base address can be remapped 1 High exception vectors Hivecs base address 0xFFFF0000 This base address is never remapped...

Page 76: ...ocation in one way exclusive caching with the L2 cache coherency mode Symmetric Multiprocessing SMP or Asymmetric Multiprocessing AMP speculative accesses on AXI broadcast of cache branch predictor and TLB maintenance operations write full line of zeros mode optimization for L2C 310 cache requests Usage constraints The ACTLR is Only accessible in privileged modes Common to the Secure and Non secur...

Page 77: ...send and receive coherent requests for Shared Inner Write back Write Allocate accesses from other Cortex A9 processors in the same coherent cluster Attributes See the register summary in Table 4 3 on page 4 6 Figure 4 9 shows the ACTLR bit assignments Figure 4 9 ACTLR bit assignments Table 4 36 shows the ACTLR bit assignments UNP SBZP 31 4 3 2 1 0 6 5 L1 Prefetch enable FW SMP 7 EXCL 8 RAZ WI 9 Pa...

Page 78: ...des support for only caching data on an eviction from L1 when the inner cache attributes are Write Back Cacheable and allocated in L1 Ensure that your cache controller is also configured for exclusive caching 0 Disabled This is the reset value 1 Enabled 6 SMP Signals if the Cortex A9 processor is taking part in coherency or not In uniprocessor configurations if this bit is set then Inner Cacheable...

Page 79: ...is UNK SBZP 30 D32DIS Disable use of D16 D31 of the VFP register file 0 All VFP instructions execute normally 1 All VFP instructions are UNDEFINED if they access any of registers D16 D31 See the Cortex A9 Floating Point Unit Technical Reference Manual and Cortex A9 NEON Media Processing Engine Technical Reference Manual for more information If implemented with VFP only this bit is RAO WI If implem...

Page 80: ...to execute any instructions that are affected by the change of access rights between the ISB and the register update To determine if any particular coprocessor exists in the system write the access bits for the coprocessor of interest with b11 If the coprocessor does not exist in the system the access rights remain set to b00 Note You must enable both coprocessor 10 and coprocessor 11 before acces...

Page 81: ...gister has no effect on Non secure access permissions for the debug control coprocessor or the system control coprocessor Configurations Available in all configurations Attributes See the register summary in Table 4 3 on page 4 6 Figure 4 12 shows the NSACR bit assignments Figure 4 12 NSACR bit assignments Table 4 38 SDER bit assignments Bits Name Function 31 2 Reserved 1 Secure User Non invasive ...

Page 82: ... UNDEFINED This is the default value 1 Non secure accesses to the CP15 c11 domain are permitted That is PLE resources are available in the Non secure state If the Preload Engine is not implemented this bit is RAZ WI See Chapter 9 Preload Engine 15 NSASEDIS Disable Non secure Advanced SIMD Extension functionality 0 This bit has no effect on the ability to write CPACR ASEDIS This is the reset value ...

Page 83: ...de FIQ Mask Override Table 4 40 VCR bit assignments Bits Name Function 31 9 UNK SBZP 8 AMO Abort Mask Override When the processor is in Non secure state and the SCR EA bit is set if the AMO bit is set this enables an asynchronous Data Abort exception to be taken regardless of the value of the CPSR A bit When the processor is in Secure state or when the SCR EA bit is not set the AMO bit is ignored ...

Page 84: ... 4 14 shows the TLB Lockdown Register bit assignments Figure 4 14 TLB Lockdown Register bit assignments Table 4 41 shows the TLB Lockdown Register bit assignments To access the TLB Lockdown Register read or write the CP15 register with MRC p15 0 Rd c10 c0 0 Read TLB Lockdown victim MCR p15 0 Rd c10 c0 0 Write TLB Lockdown victim Writing the TLB Lockdown Register with the preserve bit P bit set to ...

Page 85: ...register with MRC p15 0 Rt c11 c0 0 Read PLEIDR 4 3 17 PLE Activity Status Register The PLEASR characteristics are Purpose Indicates whether the PLE engine is active Usage constraints The PLEASR is common to Secure and Non secure states accessible in User and privileged modes regardless of any configuration bit Configurations Available in all Cortex A9 configurations regardless of whether a PLE is...

Page 86: ...y entries remain available in the PLE FIFO Usage constraints The PLEFSR is common to Secure and Non secure states accessible in User and privileged modes regardless of any configuration bit NSAC PLE controls Non secure accesses Configurations Available in all Cortex A9 configurations regardless of whether a PLE is present or not Attributes See Table 4 12 on page 4 10 Figure 4 17 shows the PLEFSR b...

Page 87: ... in configurations where the Preload Engine is present otherwise an Undefined Instruction exception is taken Attributes See Table 4 12 on page 4 10 Figure 4 18 shows the PLEUAR bit assignments Figure 4 18 PLEUAR bit assignments Table 4 45 shows the PLEUAR bit assignments To access the PLEUAR read or write the CP15 register with MCR p15 0 Rt c11 c1 0 Read PLEAUR MRC p15 0 Rt c11 c1 0 Write PLEAUR T...

Page 88: ...k size mask Permits Privilege modes to limit the maximum block size for PLE transfers The transferred block size is Block size Block size mask For example a block size mask of 14 b11111111111111 authorizes the transfer of block sizes with the maximum value of 16k 4 bytes A block size mask of 14 b00000000000000 limits block sizes to 1 4 bytes 15 8 Block number mask Permits Privilege modes to limit ...

Page 89: ...ion Interrupt Register bit assignments To access the VIR read or write the CP15 register with MRC p15 0 Rd c12 c1 1 Read Virtualization Interrupt Register MCR p15 0 Rd c12 c1 1 Write Virtualization Interrupt Register 31 0 UNK SBZP 5 6 7 8 9 UNK SBZP VA VI VF Table 4 47 Virtualization Interrupt Register bit assignments Bits Name Function 31 9 UNK SBZP 8 VA Virtual Abort bit When set the correspondi...

Page 90: ... Reserved Reserved Table 4 48 Power Control Register bit assignments Bits Name Function 31 11 Reserved 10 8 max_clk_latency Samples the value present on the MAXCLKLATENCY pins on exit from reset This value reflects an implementation specific parameter ARM strongly recommends that the software does not modify it The max_clk_latency bits determine the length of the delay between when one of these bl...

Page 91: ...gister The Configuration Base Address Register characteristics are Purpose Takes the physical base address value at reset Usage constraints The Configuration Base Address Register is read write in secure privileged modes read only in non secure state read only in User mode Configurations In Cortex A9 uniprocessor implementations the base address is set to zero In Cortex A9 MPCore implementations t...

Page 92: ...es data are written to The TLB PA register must be the last written or read register when accessing TLB lockdown registers Figure 4 24 shows the bit assignment of the index register used to access the lockdown TLB entries Figure 4 24 Lockdown TLB index bit assignments Figure 4 25 shows the bit arrangement of the TLB VA Register format Figure 4 25 TLB VA Register bit assignments Base address 31 0 T...

Page 93: ...the virtual page number that are not translated as part of the page table translation because the size of the tables is UNPREDICTABLE when read and SBZ when written 11 UNK SBZP 10 NS NS bit 9 0 Process Memory space identifier 9 8 7 0 1 UNK SBZP 0 ASID Global entries Address Space Identifier entries UNK SBZP V PPN 31 11 8 6 5 4 3 1 0 AP 12 SZ 7 UNK SBZP UNK SBZP Table 4 52 TLB PA Register bit assig...

Page 94: ...3 1 AP Access permission b000 All accesses generate a permission fault b001 Supervisor access only User access generates a fault b010 Supervisor read write access User write access generates a fault b011 Full access no fault generated b100 Reserved b101 Supervisor read only b110 Supervisor User read only b111 Supervisor User read only 0 V Value bit Indicates that this entry is locked and valid Tab...

Page 95: ...ential Chapter 5 Jazelle DBX registers This chapter introduces the CP14 coprocessor and describes the non debug use of CP14 It contains the following sections About coprocessor CP14 on page 5 2 CP14 Jazelle register summary on page 5 3 CP14 Jazelle register descriptions on page 5 4 ...

Page 96: ... 2012 ARM All rights reserved 5 2 ID073015 Non Confidential 5 1 About coprocessor CP14 The non debug use of coprocessor CP14 provides support for the hardware acceleration of Java bytecodes See the ARM Architecture Reference Manual for more information ...

Page 97: ...are zero All Jazelle registers are 32 bits wide See the ARM Architecture Reference Manual for information about the Jazelle Extension Table 5 1 CP14 Jazelle registers summary Op1 CRn Name Type Reset Page 7 0 Jazelle ID Register JIDR RWa 0xF4100168 page 5 4 7 1 Jazelle OS Control Register JOSCR RW page 5 5 7 2 Jazelle Main Configuration Register JMCR RW page 5 6 7 3 Jazelle Parameters Register RW p...

Page 98: ... clear See Jazelle Operating System Control Register on page 5 5 Configurations Available in all configurations Attributes See the register summary in Table 5 1 on page 5 3 Figure 5 1 shows the JIDR bit assignments Figure 5 1 JIDR bit assignments Table 5 2 shows the JIDR bit assignments To access the JIDR read the CP14 register with MRC p14 7 Rd c0 c0 0 Read Jazelle Identity Register 31 28 27 20 1...

Page 99: ...nts 31 2 1 0 CV CD Reserved RAZ Table 5 3 JOSCR bit assignments Bits Name Function 31 2 Reserved RAZ 1 CV Configuration Valid bit 0 The Jazelle configuration is invalid Any attempt to enter Jazelle state when the Jazelle hardware is enabled generates a configuration invalid Jazelle exception sets this bit marking the Jazelle configuration as valid 1 The Jazelle configuration is valid Entering Jaze...

Page 100: ...ay operations in hardware if implemented Otherwise call the appropriate handlers in the VM Implementation Table 1 Execute all array operations by calling the appropriate handlers in the VM Implementation Table 30 FP The FP bit controls how the Jazelle hardware executes JVM floating point opcodes 0 Execute all JVM floating point opcodes by calling the appropriate handlers in the VM Implementation T...

Page 101: ...7 IS The Index Size IS bit specifies the size of the index associated with quick object field accesses 0 Quick object field indices are 8 bits 1 Quick object field indices are 16 bits 26 SP The Static Pointer SP bit controls how the Jazelle hardware treats static references 0 Static references are treated as handles 1 Static references are treated as pointers 25 1 UNK SBZP 0 JE The Jazelle Enable ...

Page 102: ... Jazelle Configurable Opcode Translation Table Register bit assignments Table 5 5 Jazelle Parameters Register bit assignments Bits Name Function 31 22 UNK SBZP 21 17 BSH The Bounds SHift BSH bits contain the offset in bits of the array bounds number of items in the array within the array descriptor word 16 12 sADO The signed Array Descriptor Offset sADO bits contain the offset in words of the arra...

Page 103: ...n Table Register write the CP14 register with MCR p14 7 Rd c4 c0 0 Write Jazelle Configurable Opcode Translation Table Register 15 10 Opcode Contains the bottom bits of the configurable opcode 9 4 UNK SBZP 3 0 Operation Contains the code for the operation 0x0 0x9 Table 5 6 Jazelle Configurable Opcode Translation Table Register bit assignments Bits Name Function ...

Page 104: ... Non Confidential Chapter 6 Memory Management Unit This chapter describes the MMU It contains the following sections About the MMU on page 6 2 TLB Organization on page 6 4 Memory access sequence on page 6 6 MMU enabling or disabling on page 6 7 External aborts on page 6 8 ...

Page 105: ... memory The MMU enables fine grained memory system control through a set of virtual to physical address mappings and memory attributes Note In VMSAv7 first level descriptor formats page table base address bit 9 is implementation defined In Cortex A9 processor designs this bit is unused The MMU features include the following Instruction side micro TLB hardware configurable 32 or 64 fully associativ...

Page 106: ... be associated with particular processes or applications using Address Space Identifiers ASIDs ASIDs enable TLB entries to remain resident during context switches avoiding the requirement of reloading them subsequently See Invalidate TLB Entries on ASID Match on page 4 45 System control coprocessor TLB maintenance and configuration operations are controlled through a dedicated coprocessor CP15 int...

Page 107: ... granularity of a single entry As long as the lockable region does not contain any locked entries it can be allocated with non locked entries to increase overall main TLB storage size The main TLB is implemented as a combination of a fully associative lockable array of four elements a 2 way associative structure of 2x32 2x64 2x128 or 2x256 entries TLB match process Each TLB entry contains a virtua...

Page 108: ...right 2008 2012 ARM All rights reserved 6 5 ID073015 Non Confidential TLB lockdown The TLB supports the TLB lock by entry model as described in the ARM Architecture Reference Manual See TLB lockdown operations on page 4 43 for more information ...

Page 109: ...ping or a mapping for the selected ASID with a matching Non secure TLB ID NSTID for the virtual address in the TLB In this case the hardware does a translation table walk if the translation table walk is enabled by the PD0 or PD1 bit in the TTB Control Register If translation table walks are disabled the processor returns a Section Translation fault If the MMU finds a matching TLB entry it uses th...

Page 110: ...ment Unit ARM DDI 0388I Copyright 2008 2012 ARM All rights reserved 6 7 ID073015 Non Confidential 6 4 MMU enabling or disabling You can enable or disable the MMU as described in the ARM Architecture Reference Manual ...

Page 111: ...ta read or write Externally generated errors during a data read or write can be asynchronous This means that the r14_abt on entry into the abort handler on such an abort might not hold the address of the instruction that caused the exception The DFAR is UNPREDICTABLE when an asynchronous abort occurs In the case of a load multiple or store multiple operation the address captured in the DFAR is tha...

Page 112: ...escribes the L1 Memory System It contains the following sections About the L1 memory system on page 7 2 Security Extensions support on page 7 4 About the L1 instruction side memory system on page 7 5 About the L1 data side memory system on page 7 8 About DSB on page 7 10 Data prefetching on page 7 11 Parity error support on page 7 12 ...

Page 113: ...e 7 3 Cache features The Cortex A9 processor has separate instruction and data caches The caches have the following features Each cache can be disabled independently See System Control Register on page 4 25 Both caches are 4 way set associative The cache line length is eight words On a cache miss critical word first filling of the cache is performed You can configure the instruction and data cache...

Page 114: ...ache is physically indexed and physically tagged Data cache replacement policy is pseudo random Both data cache read misses and write misses are non blocking with up to four outstanding data cache read misses and up to four outstanding data cache write misses being supported Store buffer The Cortex A9 processor has a store buffer with four 64 bit slots with data merging capability ...

Page 115: ...erved 7 4 ID073015 Non Confidential 7 2 Security Extensions support The Cortex A9 processor supports the Security Extensions and exports the Secure or Non secure status of its memory requests to the memory system See the ARM Architecture Reference Manual for more information ...

Page 116: ...BTAC 2x512 entries for the 1024 entry BTAC 2x1024 entries for the 2048 entry BTAC 2x2048 entries for the 4096 entry BTAC a Global History Buffer GHB containing 1024 2048 4096 8192 or 16384 2 bit predictors implemented in RAMs a return stack with eight 32 bit entries The prediction scheme is available in ARM state Thumb state ThumbEE state and Jazelle state It is also capable of predicting state ch...

Page 117: ...m flow prediction Predicted and nonpredicted instructions Thumb state conditional branches Return stack predictions on page 7 7 Predicted and nonpredicted instructions This section shows the instructions that the processor predicts Unless otherwise specified the list applies to ARM Thumb ThumbEE and Jazelle instructions As a general rule the flow prediction hardware predicts all branch instruction...

Page 118: ...e BLX 2 register HBL ThumbEE state HBLP ThumbEE state The following instructions cause a return stack pop if predicted BX r14 MOV pc r14 LDM r13 pc LDR pc r13 The LDR instruction can use any of the addressing modes as long as r13 is the base register Additionally in ThumbEE state you can also use r9 as a stack pointer so the LDR and LDM instructions with pc as a destination and r9 as a base regist...

Page 119: ...ernal exclusive monitor The local monitor is in the Exclusive Access state after the LDREX remains in the Exclusive Access state after the STR and returns to the Open Access state only after the STREX LDREX STREX operations using different sizes In cases where the LDREX and STREX operations are of different sizes a check is performed to ensure that the tagged address bytes match or are within the ...

Page 120: ...heable all pages marked as Write Through are treated as Non Cacheable if ACTLR SMP 0 all pages marked as Shared are treated as Non Cacheable Note ARUSER 4 0 and AWUSER 4 0 directly reflect the value of the Inner attributes and Shared attribute as defined in the corresponding page descriptor They do not reflect how the Cortex A9 processor interprets them and whether the access was treated as Cachea...

Page 121: ...12 ARM All rights reserved 7 10 ID073015 Non Confidential 7 5 About DSB The Cortex A9 processor only implements the SY option of the DSB instruction All other DSB options execute as a full system DSB operation but software must not rely on this operation ...

Page 122: ...trol Register bit See Auxiliary Control Register on page 4 27 The data prefetcher can monitor and prefetch up to eight independent data streams monitors cache line requests performed by the processor cache misses and starts after a few iterations on a regular pattern either ascending or descending with a maximum stride of 8 cache lines works on confirmation and continues to prefetch and allocate t...

Page 123: ... parity generation take place in parallel RAM reads and parity checking take place in parallel in stages 3 and 4 Figure 7 2 Parity support The output signals PARITYFAIL 7 0 report parity errors Typically PARITYFAIL 7 0 reports parity errors three clock cycles after the corresponding RAM read PARITYFAIL is a pulse signal that is asserted for one CLK clock cycle 7 7 1 GHB and BTAC data corruption Th...

Page 124: ...m ARM DDI 0388I Copyright 2008 2012 ARM All rights reserved 7 13 ID073015 Non Confidential Note The Cortex A9 does not provide parity error detection support on the GHB RAMs for GHB configurations of 8192 and 16384 entries ...

Page 125: ...15 Non Confidential Chapter 8 Level 2 Memory Interface This chapter describes the L2 memory interface It contains the following sections About the Cortex A9 L2 interface on page 8 2 Optimized accesses to the L2 memory interface on page 8 7 STRT instructions on page 8 9 ...

Page 126: ...d has no write channels Table 8 1 shows the AXI master 0 interface attributes Table 8 2 shows the AXI master 1 interface attributes Table 8 1 AXI master 0 interface attributes Attribute Format Write issuing capability 12 including eight noncacheable writes four evictions Read issuing capability 10 including six linefill reads four noncacheable read Combined issuing capability 22 Write ID capabilit...

Page 127: ...cacheable transactions INCR N N 1 9 64 bit read transfers INCR 1 for 64 bit write transfers INCR N N 1 16 32 bit read transfers INCR N N 1 2 for 32 bit write transfers INCR 1 for 8 bit and 16 bit read write transfers INCR 1 for 8 bit 16 bit 32 bit 64 bit exclusive read write transfers INCR 1 for 8 bit and 32 bit read write locked for swap The following points apply to AXI transactions WRAP bursts ...

Page 128: ...XI USER bits The AXI USER bits encodings are as follows Data side read bus ARUSERM0 6 0 Table 8 3 shows the bit encodings for ARUSERM0 6 0 Instruction side read bus ARUSERM1 6 0 Table 8 4 shows the bit encodings for ARUSERM1 6 0 Table 8 3 ARUSERM0 6 0 encodings Bits Name Description 6 Reserved b0 5 L2 Prefetch hint Indicates that the read access is a prefetch hint to the L2 and does not expect any...

Page 129: ...ts evicted to L2 memory even if it is clean 5 Reserved b0 4 1 Inner attributes b0000 Strongly Ordered b0001 Device b0011 Normal Memory Non Cacheable b0110 Write Through b0111 Write Back no Write Allocate b1111 Write Back Write Allocate 0 Shared bit 0 Nonshared 1 Shared Table 8 4 ARUSERM1 6 0 encodings continued Bits Name Description Table 8 5 AWUSERM0 8 0 encodings Bits Name Description 8 Early BR...

Page 130: ...I Copyright 2008 2012 ARM All rights reserved 8 6 ID073015 Non Confidential If a line is dirty in the L2 cache controller a read request to this address from the processor causes writeback to external memory and a linefill to the processor ...

Page 131: ...cessor Programming PLE operations when this feature is available in the Cortex A9 processor In this case the PLE engine issues a series of L2 prefetch hint requests at the programmed addresses See Chapter 9 Preload Engine L2 prefetch hint requests are identified by having their ARUSER 5 bit set Note No additional programming of the L2C 310 is required 8 2 2 Early BRESP BRESP answers on response ch...

Page 132: ...of the processor but it requires a slave that is optimized for this special access The requests are marked as write full line of zeros by having the associated AWUSERM0 7 bit set Setting bit 3 of the ACTLR enables this feature See Auxiliary Control Register on page 4 27 You must program the L2C 310 Cache Controller first prior to enabling the feature in the Cortex A9 processor to support this feat...

Page 133: ... STRT instruction does not merge in the store buffer A DSB instruction is issued before and after the STRT This prevents an STRT from merging into an existing slot at the same 64 bit address or merging with another write at the same 64 bit address Table 8 6 shows Cortex A9 modes and corresponding AxPROT values Table 8 6 Cortex A9 mode and AxPROT values Processor mode Type of access Value of AxPROT...

Page 134: ... Preload Engine The design can include a Preload Engine PLE The PLE loads selected regions of memory into the L2 interface This chapter describes the PLE It contains the following sections About the Preload Engine on page 9 2 PLE control register descriptions on page 9 3 PLE operations on page 9 4 ...

Page 135: ... parameters If there is a translation abort the preload request is ignored and the Preload Engine issues the next request Not all the MMU settings are saved The Domain Tex Remap Primary Remap Normal Remap and Access Permission registers are not saved As a consequence a write operation in any of these registers causes a flush of the entire FIFO and of the active channel Additionally for TLB mainten...

Page 136: ...The following sections describe the PLE control registers PLE ID Register on page 4 36 PLE Activity Status Register on page 4 36 PLE FIFO Status Register on page 4 37 Preload Engine User Accessibility Register on page 4 38 Preload Engine Parameters Control Register on page 4 39 For all CP15 c11 system control registers NSAC PLE controls Non secure accesses PLE operations on page 9 4 shows the oper...

Page 137: ...urpose Flushes all PLE channels programmed previously including the PLE channel being executed To perform the PLE FIFO Flush operation use MCR p15 0 Rt c11 c2 1 Rt is not taken into account in this operation 9 3 2 Preload Engine pause channel operation The PLEPC operation characteristics are Purpose Pauses PLE activity You can perform a PLEPC operation even if no PLE channel is active In this case...

Page 138: ...peration use the MCRR operation MCRR p15 0 Rt Rt2 c11 Program new PLE channel Length 31 18 17 10 9 2 1 0 Stride Number of blocks RAZ WI 63 34 32 Base address VA RAZ WI 33 Table 9 1 PLE program new channel operation bit assignments Bits Name Description 63 34 Base address VA This is the 32 bit Base Virtual Address of the first block of memory to preload The address is aligned on a word boundary Tha...

Page 139: ...idential Note A newly programmed PLE entry is written to the PLE FIFO if the FIFO has available entries In cases of FIFO overflow the instruction silently fails and the FIFO Overflow event signal is asserted See Preload events in Table 11 6 on page 11 8 See PLE FIFO Status Register on page 4 37 ...

Page 140: ... application software operating systems and hardware This chapter contains the following sections Debug Systems on page 10 2 About the Cortex A9 debug interface on page 10 3 Debug register features on page 10 4 Debug register summary on page 10 5 Debug register descriptions on page 10 7 Debug management registers on page 10 13 Debug events on page 10 15 External debug interface on page 10 16 ...

Page 141: ...10 1 2 Protocol converter The debug host connects to the processor development system using an interface such as Ethernet The messages broadcast over this connection must be converted to the interface signals of the debug target A protocol converter performs this function for example RealView ICE 10 1 3 Debug target The debug target is the lowest level of the system An example of a debug target is...

Page 142: ...nce monitoring on page 2 3 and Chapter 11 Performance Monitoring Unit The debug interface consists of a Baseline CP14 interface an Extended CP14 interface an external debug interface connected to the external debugger through a Debug Access Port DAP Figure 10 2 shows the Cortex A9 debug registers interface Figure 10 2 Debug registers interface and CoreSight infrastructure Cortex A9 processor Basel...

Page 143: ...Monitoring Unit 10 3 2 Breakpoints and watchpoints The processor supports six breakpoints two with Context ID comparison BRP4 and BRP5 and four watchpoints See Breakpoint Value Registers bit functions on page 10 7 and BCR Register bit assignments on page 10 8 for more information on breakpoints See Watchpoint Value Registers bit functions on page 10 11 WCR Register bit assignments on page 10 11 an...

Page 144: ... Op1 CRm Op2 Name Type Description 0 0x000 c0 0 c0 0 DBGDIDRab RO See the ARM Architecture Reference Manual c1 0 c0 0 DBGDRARa RO c2 0 c0 0 DBGDSARa RO c0 0 c1 0 DBGDSCRintab RO 5 c0 0 c5 0 DBGDTRRXinta RO DBGDTRTXinta WO Reserved 6 0x018 c0 0 c6 0 DBGWFAR RW Use of DBGWFAR is deprecated in the ARMv7 architecture because watchpoints are synchronous 7 0x01C c0 0 c7 0 DBGVCR RW See the ARM Architect...

Page 145: ...R RO See the ARM Architecture Reference Manual 197 0x314 c1 0 c5 4 DBGPRSR RO 198 831 Reserved 832 895 0xD00 0xDFC Processor ID Registersc RO Identification Registers on page 4 12 896 927 0xE00 0xE7C Reserved 928 959 0xE80 0xEFC c7 0 c0 15 2 3 RAZ WI Reserved 960 1023 0xF00 0xFFC Debug Management Registers Debug management registers on page 10 13 a Baseline CP14 interface This register also has an...

Page 146: ...D value an IVA and context ID pair For an IVA and context ID pair two BRPs must be linked A debug event is generated when both the IVA and the context ID pair match at the same time Table 10 3 shows how the bit values correspond with the Breakpoint Value Registers functions Note Only BRP4 and BRP5 support context ID comparison BVR0 1 0 BVR1 1 0 BVR2 1 0 and BVR3 1 0 are Should Be Zero or Preserved...

Page 147: ...scription 31 29 RAZ on reads SBZP on writes 28 24 Breakpoint address mask Breakpoint address mask RAZ WI b00000 No mask 23 RAZ on reads SBZP on writes 22 20 M Meaning of BVR b000 Instruction virtual address match b001 Linked instruction virtual address match b010 Unlinked context ID b011 Linked context ID b100 Instruction virtual address mismatc h b101 Linked instruction virtual address mismatch b...

Page 148: ...sed b1100 Hits if any of the two bytes starting at address BVR 0xFFFFFFFC 2 is accessed b1111 Hits if any of the four bytes starting at address BVR 0xFFFFFFFC 0 is accessed If you program the BRP for IVA mismatch the breakpoint hits where the corresponding IVA breakpoint does not hit that is the range of addresses covered by an IVA mismatch breakpoint is the negative image of the corresponding IVA...

Page 149: ...th any other one It generates a breakpoint debug event on a joint context ID and state match For this BRP BCR 8 5 must be set to b1111 Otherwise it is UNPREDICTABLE whether a breakpoint debug event is generated b011 The corresponding BVR 31 0 is compared against CP15 Context ID Register c13 This BRP links another BRP of the BCR 21 20 b01 type or WRP with WCR 20 b1 They generate a breakpoint or wat...

Page 150: ...ssignments Table 10 7 Watchpoint Value Registers bit functions Bits Name Description 31 2 Watchpoint address 1 0 RAZ on reads SBZP on writes Reserved Linked BRP L S W Reserved Watchpoint address mask 31 21 20 19 16 15 5 3 2 1 E SP 24 4 0 14 13 29 28 23 Secure state access control 12 RAZ SBZP on writes 8 9 Reserved Byte address select Table 10 8 WCR Register bit assignments Bits Name Description 31...

Page 151: ... exclusive or swap b10 Store store exclusive or swap b11 Either SWP and SWPB trigger a watchpoint on b01 b10 or b11 A load exclusive instruction triggers a watchpoint on b01 or b11 A store exclusive instruction triggers a watchpoint on b10 or b11 only if it passes the local monitor within the processor a 2 1 SP Privileged access control The watchpoint can be conditioned to the privilege of the acc...

Page 152: ...heral Identification Registers are accessible from the Debug APB bus Only bits 7 0 of each register are used The remaining bits are Read As Zero The values in these registers are fixed Table 10 9 Debug management registers Register number Offset Name CRn Op1 CRm OP2 Type Description 960 0xF00 DBGITCTRL c7 0 c0 4 RAZ WI Integration Mode Control Register 961 999 0xF04 0xF9C RAZ Reserved 1000 0xFA0 D...

Page 153: ...are associated with each Component Identification Register See the ARM Debug Interface v5 Specification for more information on the Peripheral ID Registers Table 10 10 Peripheral Identification Register Summary Register number Offset Name Type Value Description 1012 0xFD0 DBGPID4 RO 0x04 Peripheral Identification Register 4 1013 0xFD4 DBGPID5 RO Reserved 1014 0xFD8 DBGPID6 RO Reserved 1015 0xFDC D...

Page 154: ...ts A watchpoint event is always synchronous It has the same behavior as a synchronous data abort The method of debug entry DBGDSCR 5 2 never has the value b0010 If a synchronous abort occurs on a watchpointed access the synchronous abort takes priority over the watchpoint If the abort is asynchronous and cannot be associated with the access the exception that is taken is UNPREDICTABLE Cache mainte...

Page 155: ...ignals Figure 10 5 External debug interface signals 10 8 1 Debugging modes Authentication signals control the debugging modes The authentication signals configure the processor so its activity can only be debugged or traced in a certain subset of processor modes and security states See Authentication signals on page 10 17 Note The Cortex A9 processor only supports halting debug mode debugging in s...

Page 156: ...ipheral 2 If step 1 involves any memory operation issue a DSB Table 10 12 Authentication signal restrictions SPIDEN DBGENa SPNIDEN NIDEN Secureb invasive debug permitted Non secure invasive debug permitted Secure non invasive debug permitted Non secure non invasive debug permitted 0 0 0 0 No No No No 0 0 0 1 No No No Yes 0 0 1 0 No No No No 0 0 1 1 No No Yes Yes 0 1 0 0 No Yes No Yes 0 1 0 1 No Ye...

Page 157: ...8 5 External debug request interface The following sections describe the external debug request interface signals EDBGRQ DBGACK DBGCPUDONE COMMRX and COMMTX on page 10 19 DBGROMADDR and DBGSELFADDR on page 10 19 EDBGRQ This signal generates a halting debug event to request the processor to enter debug state When this occurs the DSCR 5 2 method of debug entry bits are set to b0100 When EDBGRQ is as...

Page 158: ...0 DTRRX full flag COMMTX is asserted when the CP14 is ready for write data and it is deasserted when the processor writes the data Its value ia equal to the inverse of the DBGDSCR 29 DTRTX full flag DBGROMADDR and DBGSELFADDR The Cortex A9 processor has a memory mapped debug interface The processor can access the debug and PMU registers by executing load and store instructions through the AXI bus ...

Page 159: ...nce Monitoring Unit This chapter describes the Performance Monitoring Unit PMU and the registers that it uses It contains the following sections About the Performance Monitoring Unit on page 11 2 PMU register summary on page 11 3 PMU management registers on page 11 5 Performance monitoring events on page 11 7 ...

Page 160: ... reserved 11 2 ID073015 Non Confidential 11 1 About the Performance Monitoring Unit The Cortex A9 PMU provides six counters to gather statistics on the operation of the processor and memory system Each counter can count any of the 58 events available in the Cortex A9 processor ...

Page 161: ...EVCNTR4 RW 5 0x014 c9 0 c13 2 PMXEVCNTR5 RW 6 30 0x018 0x078 Reserved 31 0x07C c9 0 c13 0 PMCCNTR RW Cycle Count Register see the ARM Architecture Reference Manual 32 255 0x080 0x3FC Reserved 256 0x400 c9 0 c13 1 PMXEVTYPER0 RW Event Type Selection Register see the ARM Architecture Reference Manual 257 0x404 c9 0 c13 1 PMXEVTYPER1 RW 258 0x408 c9 0 c13 1 PMXEVTYPER2 RW 259 0x40C c9 0 c13 1 PMXEVTY...

Page 162: ... Increment Register see the ARM Architecture Reference Manual 809 831 0xCA4 0xCFC Reserved 832 895 896 0xE00 Reserved 897 0xE04 c9 0 c12 0 PMCR RW Performance Monitor Control Register see the ARM Architecture Reference Manual 898 0xE08 c9 0 c14 0 PMUSERENR RWa User Enable Register see the ARM Architecture Reference Manual c9 0 c12 5 PMSELR RW Event Counter Select Register see the ARM Architecture ...

Page 163: ...e 11 3 shows the register number offset value name type value and description that are associated with each PMU Peripheral Identification Register Table 11 2 PMU management registers Register number Offset Name Type Description 960 0xF00 PMITCTRL RAZ WI Integration Mode Control Register 961 999 0xF04 0xF9C RAZ Reserved 1000 0xFA0 PMCLAIMSET RW Claim Tag Set Register 1001 0xFA4 PMCLAIMCLR RW Claim ...

Page 164: ...and value that are associated with each PMU Component Identification Register See the ARM Debug Interface v5 Specification for more information on the Component ID Registers 1016 0xFE0 PMPID0 RO 0xA0 Peripheral Identification Register 0 1017 0xFE4 PMPID1 RO 0xB9 Peripheral Identification Register 1 1018 0xFE8 PMPID2 RO 0x0B Peripheral Identification Register 2 1019 0xFEC PMPID3 RO 0x00 Peripheral ...

Page 165: ...mber Event 0x00 Software increment 0x01 Instruction cache miss 0x02 Instruction micro TLB miss 0x03 Data cache miss 0x04 Data cache access 0x05 Data micro TLB miss 0x06 Data read 0x07 Data writes 0x08a a This event is not implemented However similar functionality is provided by event number 0x68 Instructions coming out of the core renaming stage See Table 11 6 on page 11 8 0x09 Exception taken 0x0...

Page 166: ...ta is fetched directly from the relevant Cortex A9 cache Precise 0x60 Instruction cache dependent stall cycles Counts the number of cycles where the processor is ready to accept new instructions does not receive a new instruction because the instruction side is unable to provide one the instruction cache is performing at least one linefill Approximate 0x61 Data cache dependent stall cycles Counts ...

Page 167: ... in prefetched cache lines c Counts the number of cache hits in a line that belongs to a stream followed by the prefetcher This includes lines that have been prefetched by the automatic data prefetcher lines already present in the cache before the prefetcher action Precise 0x6E Predictable function returns Counts the number of procedure returns whose condition codes do not fail excluding all retur...

Page 168: ...s full and executes writes to the external memory Approximate 0x82 Processor stalled because of instruction side main TLB miss Counts the number of stall cycles because of main TLB misses on requests issued by the instruction side Approximate 0x83 Processor stalled because of data side main TLB miss Counts the number of stall cycles because of main TLB misses on requests issued by the data side Ap...

Page 169: ...DMB instructions speculatively executed Approximate 0x93 External interrupts Counts the number of external interrupts executed by the processor Approximate 0xA0 PLE cache line request completed d Precise 0xA1 PLE cache line request skipped d Precise 0xA2 PLE FIFO flush d Precise 0xA3 PLE request completed d Precise 0xA4 PLE FIFO overflow d Precise 0xA5 PLE request programmed d Precise a Only when ...

Page 170: ... Reset signals on page A 3 Interrupts on page A 4 Configuration signals on page A 5 WFE and WFI standby signals on page A 6 Power management signals on page A 7 AXI interfaces on page A 8 Performance monitoring signals on page A 14 Exception flags signal on page A 17 Parity signal on page A 18 MBIST interface on page A 19 Scan test signal on page A 20 External Debug interface on page A 21 PTM inte...

Page 171: ...bal clock Table A 1 shows the clock and clock control signals Table A 1 Clock and clock control signals Name I O Source Description CLK I Clock controller Global clock See Clocking and resets on page 2 6 MAXCLKLATENCY 2 0 I Implementation specific static value Controls dynamic clock gating delays This pin is sampled during reset of the processor See Power Control Register on page 4 41 ...

Page 172: ...ol signals See Reset on page 2 6 Table A 2 Reset signals Name I O Source Description nCPURESET I Reset controller Cortex A9 processor reset nDBGRESET I Cortex A9 processor debug logic reset NEONCLKOFFa a Only if the MPE is present I MPE SIMD logic clock control 0 Do not cut MPE SIMD logic clock 1 Cut MPE SIMD logic clock nNEONRESETa I Cortex A9 MPE SIMD logic reset ...

Page 173: ...ption nFIQ I Interrupt sources Cortex A9 processor FIQ request input line Active LOW fast interrupt request 0 Activate fast interrupt 1 Do not activate fast interrupt The processor treats the nFIQ input as level sensitive nIRQ I Interrupt sources Cortex A9 processor IRQ request input line Active LOW interrupt request 0 Activate interrupt 1 Do not activate interrupt The processor treats the nIRQ in...

Page 174: ... interrupts to be non maskable 0 Clear the NMFI bit in the CP15 c1 Control Register 1 Set the NMFI bit in the CP15 c1 Control Register TEINIT I Default exception handling state 0 ARM 1 Thumb This signal sets the SCTLR TE bit at reset VINITHI I Controls the location of the exception vectors at reset 0 Start exception vectors at address 0x00000000 1 Start exception vectors at address 0xFFFF0000 This...

Page 175: ...ion Description EVENTI I External coherent agent Event input for Cortex A9 processor wake up from WFE mode EVENTO O Event output This signal is active HIGH for one processor clock cycle when an SEV instruction is executed STANDBYWFE O Power controller Indicates if the processor is in WFE mode 0 Processor not in WFE standby mode 1 Processor in WFE standby mode STANDBYWFI O Indicates if the processo...

Page 176: ...he power management signals See Power management on page 2 10 Table A 7 Power management signals Name I O Source Description CPURAMCLAMP I Power controller Activates the CPU RAM interface clamps 0 Clamps not active 1 Clamps active NEONCLAMPa a Only if the MPE is present I Activates the Cortex A9 MPE SIMD logic clamps 0 Clamps not active 1 Clamps active ...

Page 177: ...ata channel signals on page A 9 Write response channel signals on page A 10 Read address channel signals for AXI Master0 on page A 10 Read data channel signals on page A 11 AXI Master0 Clock enable signals on page A 11 Write address channel signals for AXI Master0 Table A 8 shows the AXI write address channel signals for AXI Master0 Table A 8 Write address channel signals for AXI Master0 Name I O ...

Page 178: ...BRESP Used with L2C 310 7 write full line of zeros Used with the L2C 310 6 clean eviction 5 level 1 eviction 4 1 memory type and Inner cache policy b0000 Strongly ordered b0001 Device b0011 Normal Memory Non Cacheable b0110 Write Through b0111 Write Back no Write Allocate b1111 Write Back Write Allocate 0 shared AWVALIDM0 O Address valid Table A 8 Write address channel signals for AXI Master0 cont...

Page 179: ...me I O Source or destination Description ARADDRM0 31 0 O AXI system devices Address ARBURSTM0 1 0 O Burst type b001 INCR incrementing burst b010 WRAP Wrapping burst ARCACHEM0 3 0 O Cache type giving additional information about cacheable characteristics ARIDM0 1 0 O Request ID ARLENM0 3 0 O The number of data transfers that can occur within each burst ARLOCKM0 1 0 O Lock type ARPROTM0 2 0 O Protec...

Page 180: ...or instruction accesses Read address channel signals for AXI Master1 on page A 12 Read data channel signals on page A 13 AXI Master1 Clock enable signals on page A 13 Table A 12 Read data channel signals for AXI Master0 Name I O Source or destination Description RVALIDM0 I AXI system devices Read valid RDATAM0 63 0 I Read data RRESPM0 1 0 I Read response RLASTM0 I Read last indication RIDM0 1 0 I ...

Page 181: ...CHEM1 3 0 O Cache type giving additional information about cacheable characteristics ARIDM1 5 0 O Request ID ARLENM1 3 0 O The number of data transfers that can occur within each burst ARLOCKM1 1 0 O Lock type b00 Normal access ARPROTM1 2 0 O Protection type ARREADYM1 I Address ready ARSIZEM1 1 0 O AXI system devices Burst size b000 8 bit transfer b001 16 bit transfer b010 32 bit transfe r b011 64...

Page 182: ... Interface Table A 15 AXI R signals for AXI Master1 Name I O Source or destination Description RVALIDM1 I AXI system devices Read valid RDATAM1 63 0 I Read data RRESPM1 1 0 I Read response RLASTM1 I Read last indication RIDM1 5 0 I Read ID RREADYM1 O Read ready Table A 16 Clock enable signal for AXI Master1 Name I O Source Description ACLKENM1 I Clock controller Clock enable for the AXI bus that e...

Page 183: ... status of the Cortex A9 processor 0 In User mode 1 In Privileged mode This signal does not provide input to CoreSight trace delivery infrastructure Table A 18 Event signals and event numbers Name Event number Description PMUEVENT 0 0x00 Software increment PMUEVENT 1 0x01 Instruction cache miss PMUEVENT 2 0x02 Instruction micro TLB miss PMUEVENT 3 0x03 Data cache miss PMUEVENT 4 0x04 Data cache ac...

Page 184: ...T 30 0x66 Issue does not dispatch any instruction PMUEVENT 31 0x67 Issue is empty PMUEVENT 32 0x70 Main Execution Unit pipe PMUEVENT 33 0x71 Second Execution Unit pipe PMUEVENT 34 0x72 Load Store pipe PMUEVENT 35 0x73 b00 No floating point instruction renamed b01 One floating point instruction renamed b10 Two floating point instructions renamed PMUEVENT 36 PMUEVENT 37 0x74 b00 No NEON instructions...

Page 185: ... 0xA0 PLE cache line request completed PMUEVENT 53 0xA1 PLE cache line request skipped PMUEVENT 54 0xA2 PLE FIFO Flush PMUEVENT 55 0xA3 PLE request completed PMUEVENT 56 0xA4 PLE FIFO Overflow PMUEVENT 57 0xA5 PLE request programmed a Not generated by Cortex A9 processors Replaced by the similar event 0x68 b Not generated by Cortex A9 processors Replaced by the similar event 0x6E c Used in multipr...

Page 186: ...x A9 NEON Media Processing Engine Technical Reference Manual Table A 19 DEFLAGS signal Name I O Destination Description DEFLAGS 6 0 O Exception monitoring unit Data engine output flags Only implemented if the Cortex A9 processor includes a Data engine either an MPE or FPU If the DE is MPE Bit 6 gives the value of FPSCR 27 Bit 5 gives the value of FPSCR 7 Bits 4 0 give the value of FPSCR 4 0 If the...

Page 187: ...t on page 7 12 Table A 20 Parity signal Name I O Destination Description PARITYFAIL 7 0 O Parity monitoring device Parity output pin from the RAM arrays 0 No parity fail 1 Parity fail Bit 7 BTAC parity error Bit 6 GHB parity error Bit 5 instruction tag RAM parity error Bit 4 instruction data RAM parity error Bit 3 main TLB parity error Bit 2 data outer RAM parity error Bit 1 data tag RAM parity er...

Page 188: ...f MBIST Table A 21 MBIST interface signals Name I O Source Description MBISTADDR 10 0 I MBIST controller MBIST address bus MBISTARRAY 19 0 I MBIST arrays used for testing RAMs MBISTENABLE I MBIST test enable MBISTWRITEEN I Global write enable MBISTREADEN I Global read enable Table A 22 MBIST signals with parity support implemented Name I O Source or destination Description MBISTBE 32 0 I MBIST con...

Page 189: ...t 2008 2012 ARM All rights reserved A 20 ID073015 Non Confidential A 12 Scan test signal Table A 24 shows the scan test signal Table A 24 Scan test signal Name I O Destination Description SE I DFT controller Scan enable 0 Not enabled 1 Enabled ...

Page 190: ... Miscellaneous debug interface signals on page A 23 A 13 1 Authentication interface Table A 25 shows the authentication interface signals Table A 25 Authentication interface signals Name I O Source Description DBGEN I Security controller Invasive debug enable 0 Not enabled 1 Enabled NIDEN I Non invasive debug enable 0 Not enabled 1 Enabled SPIDEN I Secure privileged invasive debug enable 0 Not ena...

Page 191: ...TADBG 31 0 O APB read data bus PREADYDBG O APB slave ready An APB slave can assert PREADY to extend a transfer PSLVERRDBG O APB slave error signal Table A 27 CTI signals Name I O Source or destination Description EDBGRQ I External debugger or CoreSight interconnect External debug request 0 No external debug request 1 External debug request The processor treats the EDBGRQ input as level sensitive T...

Page 192: ...ger The debugger has requested that the Cortex A9 processor is not powered down DBGSWENABLE I External debugger When LOW only the external debug agent can modify the debug registers 0 Not enabled 1 Enabled DBGROMADDR 31 12 I System configuration Specifies bits 31 12 of the ROM table physical address If the address cannot be determined tie this signal LOW DBGROMADDRV I Valid signal for DBGROMADDR I...

Page 193: ...committed in this cycle It is valid to indicate a valid waypoint and commit it in the same cycle WPTCONTEXTID 31 0 O Context ID for the waypoint This signal must be true regardless of the condition code of the waypoint If the processor Context ID has not been set then WPTCONTEXTID 31 0 must report 0 WPTENABLE I Enable waypoint WPTEXCEPTIONTYPE 3 0 O Exception type b0001 Halting debug mode b0010 Se...

Page 194: ...bit for waypoint destination WPTTRACEPROHIBITED O PTM device Trace is prohibited for the waypoint target Indicates entry to prohibited region No more waypoints are traced until trace can resume This signal must be permanently asserted if NIDEN and DBGEN are both LOW after the in flight waypoints have exited the processor Either an exception or a serial branch is required to ensure that changes to ...

Page 195: ...tions following the waypoint are executed in Non secure state An instruction is in Non secure state if the NS bit is set and the processor is not in secure monitor mode See About system control on page 4 2 for information about Security Extensions WPTFIFOEMPTY O There are no speculative waypoints in the PTM interface FIFO Table A 29 PTM interface signals continued Name I O Source or destination De...

Page 196: ...ter describes the cycle timings of integer instructions on Cortex A9 processors It contains the following sections About instruction cycle timing on page B 2 Data processing instructions on page B 3 Load and store instructions on page B 4 Multiplication instructions on page B 7 Branch instructions on page B 8 Serializing instructions on page B 9 ...

Page 197: ... code sequences require The complexity of the Cortex A9 processor makes it impossible to calculate precise timing information manually The timing of an instruction is often affected by other concurrent instructions memory system activity and additional events outside the instruction flow Detailed descriptions of all possible instruction interactions and all possible events taking place in the proc...

Page 198: ...structions cycle timings Instruction No shift Shift by Constant Register MOV 1 1 2 AND EOR SUB RSB ADD ADC SBC RSC CMN ORR BIC MVN TST TEQ CMP 1 2 3 QADD QSUB QADD8 QADD16 QSUB8 QSUB16 SHADD8 SHADD16 SHSUB8 SHSUB16 UQADD8 UQADD16 UQSUB8 UQSUB16 UHADD8 UHADD16 UHSUB8 UHSUB16 QASX QSAX SHASX SHSAX UQASX UQSAX UHASX UHSAX 2 QDADD QDSUB SSAT USAT 3 PKHBT PKHTB 1 2 SSAT16 USAT16 SADD8 SADD16 SSUB8 SSUB...

Page 199: ...sing instruction is an arithmetical a logical or a saturation operation the data processing instruction does not require any shift the load instruction does not require sign extension the load instruction is not conditional Table B 2 shows cycle timing for single load and store operations The result latency is the latency of the first loaded register Table B 2 Single load and store operation cycle...

Page 200: ...sulting latency is the latency of the first loaded register Table B 3 shows the cycle timings for load multiple operations Table B 3 Load multiple operations cycle timings Instruction AGU cycles to process the instruction Resulting latency Address aligned on a 64 bit boundary Fast forward case Other cases Yes No LDM 1 register 1 1 2 3 LDM 2 registers LDRD RFE 1 2 2 3 LDM 3 registers 2 2 2 3 LDM 4 ...

Page 201: ...erations cycle timings Instruction AGU cycles Aligned on a 64 bit boundary Yes No STM 1 register 1 1 STM 2 registers STRD SRS 1 2 STM 3 registers 2 2 STM 4 registers 2 3 STM 5 registers 3 3 STM 6 registers 3 4 STM 7 registers 4 4 STM 8 registers 4 5 STM 9 registers 5 5 STM 10 registers 5 6 STM 11 registers 6 6 STM 12 registers 6 7 STM 13 registers 7 7 STM 14 registers 7 8 STM 15 registers 8 8 STM ...

Page 202: ...ult latency MUL S MLA S 2 4 SMULL S UMULL S SMLAL S UMLAL S 3 4 for the first written register 5 for the second written register SMULxy SMLAxy SMULWy SMLAWy 1 3 SMLALxy 2 3 for the first written register 4 for the second written register SMUAD SMUADX SMLAD SMLADX SMUSD SMUSDX SMLSD SMLSDX 1 3 SMMUL SMMULR SMMLA SMMLAR SMMLS SMMLSR 2 4 SMLALD SMLALDX SMLSLD SMLDLDX 2 3 for the first written registe...

Page 203: ...tions do not consume execution unit cycles Data processing instructions to the PC register are processed in the execution units as standard instructions See Data processing instructions on page B 3 Load instructions to the PC register are processed in the execution units as standard instructions See Load and store instructions on page B 4 See About the L1 instruction side memory system on page 7 5...

Page 204: ...g exception entry instructions are serializing SVC SMC BKPT instructions that take the prefetch abort handler instructions that take the Undefined Instruction exception handler The following instructions that modify mode or program control are serializing MSR CPSR when they modify control or mode bits data processing to PC with the S bit set for example MOVS pc r14 LDM pc CPS SETEND RFE The follow...

Page 205: ...dress generation Figure 1 1 on page 1 2 Changed fast loop mode to small loop mode Figure 1 1 on page 1 2 Small loop mode on page 1 3 Instruction cache features on page 7 2 About power consumption control on page 12 6 Changed branch prediction to dynamic branch prediction Features on page 1 6 About the L1 instruction side memory system on page 7 5 Branch instructions on page B 8 Changed LI cache co...

Page 206: ...BR0 TTRBR1 Main TLB on page 6 4 Added note about invalidating the caches and BTAC before use About the L1 memory system on page 7 2 Added parity support scheme information section Parity error support on page 7 12 Listed and described L2 master interfaces M0 and M1 Cortex A9 L2 interface on page 8 2 Added cross reference to DBSCR external description Extended footnote to include reference to the D...

Page 207: ...ns Auxiliary Control Register on page 4 64 Added information about a second replacement strategy Selection done by SCTLR RR bit System Control Register on page 4 25 Extended event information Cortex A9 specific events on page 4 32 Added DEFLAGS 6 0 DEFLAGS 6 0 on page 4 37 Performance monitoring signals on page A 14 Added Power Control Register description Power Control Register on page 4 63 Added...

Page 208: ...Added nWDRESET Added nPERIPHRESET Changed voltage domain boundaries and description Figure 2 4 on page 2 14 2 5 4 Date Engine logic reset replaced MPE SIMD logic reset on page 2 8 Cortex A9 input signals DECLAMP removed level shifters reference removed Communication to the power management controller on page 2 13 Table 3 1 J and T bit encoding removed The Jazelle extension on page 3 3 moved The Ja...

Page 209: ...ache controller behavior Early BRESP on page 8 7 Write full line of zeros signal name corrected to AWUSERM0 7 Write full line of zeros on page 8 8 Speculative coherent requests section added Speculative coherent requests on page 8 8 Removed sentence about tying unused bits of PARITYFAIL HIGH Parity error support on page 7 12 Added PE description Chapter 9 Preload Engine Added PMU description Chapt...

Page 210: ... name corrected Table 4 2 on page 4 5 Descriptions clarified and footnote added Table 4 30 on page 4 20 Purpose description extended Cache Size Identification Register on page 4 21 System Control Register value corrected and footnotes amended Table 4 3 on page 4 6 Bit 17 function corrected Table 4 35 on page 4 25 Footnote d corrected Table 4 15 on page 4 11 Purpose description extended Power Contr...

Page 211: ...nformation repeated from AXI removed Table A 11 on page A 10 ARLENM0 3 0 ARLOCKM0 1 0 Title changed AXI Master1 signals instruction accesses on page A 11 Information repeated from AXI removed Table A 14 on page A 12 ARLENM1 3 0 PMUEVENT 46 and PMUEVENT 47 corrected Table A 17 on page A 14 Introduction reduced and note about DSB behavior added Serializing instructions on page B 9 Table C 5 Differen...

Page 212: ...from debug registers summary to debug management registers Table 10 1 on page 10 5 Table 10 9 on page 10 13 All revisions Update description of debug management registers Debug management registers on page 10 13 All revisions Update description of DBGITCTRL and DBGDEVID registers Table 10 9 on page 10 13 All revisions Update description of external debug interface External debug interface on page ...

Page 213: ...the L1 instruction side memory system on page 7 5 r4p0 Added description of an enhanced data prefetching mechanism Data prefetching on page 7 11 r4p0 Updated parity error support description Parity error support on page 7 12 r4p0 Updated description of PLE Program New Channel operation PLE Program New Channel operationon page 9 5 All revisions Updated heading of table describing Meaning of BVR as ...

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