ADSP-21065L SHARC User’s Manual 1-1
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Figure 1-0.
Table 1-0.
Listing 1-0.
The ADSP-21065L SHARC is a high-performance, 32-bit digital signal
processor for communications, digital audio, and industrial instrumenta-
tion applications.
Along with a high-performance, 180 MFLOPS core, the ADSP-21065L
has a dual-ported, on-chip SRAM and integrated I/O peripherals sup-
ported by a dedicated I/O processor. With its on-chip instruction cache,
the processor can execute every instruction in a single cycle. The
ADSP-21065L is code-compatible with other members of the SHARC
family.
Four independent buses for dual data, instructions, and I/O, and cross-
bar-switch memory connections implement the ADSP-21065L’s Super
Harvard Architecture.
The ADSP-21065L provides these features:
• 32-Bit IEEE floating-point computation units—Multiplier, ALU,
and Shifter—that support 180 MFLOPS or 180, 32-bit fixed-point
MOPS.
• Data Register File.
• Data Address Generators (DAG1, DAG2).
• Program Sequencer with Instruction Cache.
• 544 Kbits of user-configurable, dual-ported SRAM.
• External port for glueless interface to SDRAM and other off-chip
memory and peripherals.
