UG-1698
Rev. 0 | Page 20 of 23
As an initial debug step, power cycle all hardware, reopen the
software, reopen the
DPGDownloader
software, and
follow the evaluation board configuration instructions in the
Hardware Setup section.
The following are some debugging suggestions for when the
serializer/deserializer (SERDES) link does not come up:
Check to ensure that the
DPGDownloader
software is
configured to play a particular signal vector (sometimes
called a pattern), the pattern is downloaded to the
is attempting to
play this pattern to the evaluation board. The
attempts to establish a JESD204B link only after a pattern is
selected and the
SYNCOUT± line is asserted. The
does not monitor the SYNCOUT± line if a
pattern is not downloaded onto its memory.
SYNCOUT± status is monitored by the
DPGDownloader
software through the
, and its status is indicated
next to SYNC Status: a green check mark means the
SYNCOUT± is high and the link is properly synchronized
and that it is currently running. A red cross means the
SYNCOUT± signal is low and the AD9166 is ready for the
to begin synchronization. A yellow exclama-
tion means the SYNCOUT± signal is toggling, which
indicates that an IRQ has occurred or that the link is unstable
and synchronization cannot be reliably achieved. Typically, a
yellow exclamation implies that either the data rate was not
configured to match between
and the
DPGDownloader
software, or there is a bad connection on one of the used
SERDES lanes. Check the FMC connector and make sure
the
Data Rate
values in both
and
DPGDownloader
software match.
Check that the correct JESD204B Subclass is selected. Only
Subclass 0 or Subclass 1 is supported. Subclass 0 is selected
by default. If Subclass 1 is selected for
while
configuring the evaluation board for Subclass 0, the
waits indefinitely for a SYSREF± clock to be
provided by the evaluation board. The evaluation board
provides SYSREF± only when it is configured for Subclass 1,
with SYSREF± generated by the
. SYSREF±
cannot be provided to the
externally
through an SMA connector on the evaluation board and
without using the on-board
clocking IC.
Ensure that the JESD204B
Line Rate
displayed by the
DPGDownloader
is reflecting the line rate that
reports. The line rate, sometimes referred to as the lane
rate or bit rate, is the rate at which encoded data is sampled
across the SERDES lanes. This sampling clock must be
generated at both the transmitter and receiver of the
JESD204B link. The JESD204B transmitter of the
relies on an internal PLL that uses a
reference at a rate equal to lane rate/40. The JESD204B
receiver of the
relies on an internal PLL that uses
the DAC clock as a reference. For more details, see the
Evaluation Board Hardware section of this user guide and
the
data sheet.
Before configuring the AD9166-FMC-EBZ evaluation board, it
is a good practice to soft reset the evaluation board by clicking
the
Reset Board
button in the evaluation board view of
Figure 12), or by clicking the
Reset Chip
button in the chip view
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32
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20
Figure 20.
Reset Chip
in Chip View
Does Not Recognize the Evaluation Board
One of two possible errors can be generated, as shown in Figure 21
and Figure 22. Both error messages indicate that the
software did not recognize the AD9166-FMC-EBZ evaluation
board.
to facilitate a connection (a
bridge) to the SPI bus of the evaluation board. If the correct
image was not uploaded onto the
by the
DPGDownloader
is not able to communicate to
the AD9166-FMC-EBZ evaluation board.
The sequence of events may matter. Some errors occur if the
software is started before powering up and connecting the
evaluation board to the PC, or when the evaluation board is
power cycled and
is not restarted. The simplest remedy is
to power up all hardware, open
DPGDownloader
, allow the
to be loaded, and only then open
configure the AD9166-FMC-EBZ.
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Figure 21. Script Error Window Indicating
Does Not Recognize the
Evaluation Board
