background image

AD9166-FMC-EBZ

 User Guide 

UG-1698

 

Rev. 0 | Page 15 of 23 

9.

 

Generate and download other vectors after the JESD204B 
link is up. 

10.

 

Repeat Step 2 to Step 6 to run a new setting, such as a 
different clock rate, interpolation ratio, lanes, or reference 
clock. 

See the Troubleshooting section for debug information (if the 
link disappears). 

If the interpolation is equal to 1, the 

DPGDownloader

 software 

displays a single tone in the 

Vector

 dropdown box, as shown in 

Figure 15. The data type is real only (not complex) and 

Interpolation Mode

 is set to 

1X

If the interpolation is greater than 1, two 

Vector

 dropdown 

boxes are displayed in the 

Data Playback

 section to allow 

downloading a complex data vector, comprising an inphase (I) 
and quadrature (Q) vector of equal length. The data type is 
complex, and 

Interpolation Mode

 is set to 

>1X

 

22

32

4-

01

5

 

Figure 15. Download Single Tone and Play 

Summary of Contents for AD9166-FMC-EBZ

Page 1: ...link which simplifies evaluation of the device The evaluation board is powered by the field programmable gate array FPGA mezzanine card FMC power supply provided through the ADS7 V2EBZ Figure 1 shows...

Page 2: ...l Clock 6 Configuration 2 On Board Clock 6 Configuration 3 NCO Only 6 Getting Started 7 Initial Setup 7 DC Test NCO Mode 8 Configure the Spectrum Analyzer 8 Configure the Evaluation Board 8 Using the...

Page 3: ...p bandwidth of PLL1 results in a longer lock time if the input reference frequency is considerably lower than the oscillator frequency to which the PLL attempts to lock On the AD9166 FMC EBZ evaluatio...

Page 4: ...EBZ cannot be configured to generate an external SYSREF signal to the FMC connector External DAC clock connected to J4 with a low frequency external reference connected to J61 The reference is then ro...

Page 5: ...ter map of the AD9166 and has additional functionality such as the ability to record load and save macros or register sequences to ease programming of the device Use the DPGDownloader program for load...

Page 6: ...66 FMC EBZ is routed through the FMC connector and either an ADS7 V2EBZ or an FPGA development kit must be connected to the evaluation board to send SPI commands As a workaround short wires can be sol...

Page 7: ...Guide section Download this software online from the ACE software page The ACE software package includes the required plugins for the AD9166 FMC EBZ evaluation board INITIAL SETUP Complete the followi...

Page 8: ...e 5 3 Open the evaluation board view by double clicking the AD9166 FMC EBZ evaluation board icon as shown in Figure 5 4 In the AD9166 STARTUP WIZARD under Board Clocking Schemes select All internal cl...

Page 9: ...AD9166 FMC EBZ User Guide UG 1698 Rev 0 Page 9 of 23 22324 006 Figure 6 ACE Initial Configuration 22324 007 Figure 7 AD9166 Chip View and Clock Source Selection in ACE...

Page 10: ...UG 1698 AD9166 FMC EBZ User Guide Rev 0 Page 10 of 23 22324 008 Figure 8 Spectrum Analyzer Plot of DAC Output in NCO Mode Showing a Single Tone at 1 GHz...

Page 11: ...omplete the following steps to configure the ADS7 V2EBZ board and load a single tone at 800 MHz to the on board FPGA 1 To load and play the pattern to the ADS7 V2EBZ open DPGDownloader from Start Prog...

Page 12: ...oder Sending 16 bit data this way can improve spurious performance compared to sending 11 bit data 8 Enter 800 MHz in Desired Frequency 9 Keep 0 0 dB in Amplitude 10 Clear the Unsigned Data box becaus...

Page 13: ...5 3 Using the AD9166 STARTUP WIZARD on the left side of the window follow these steps as shown in Figure 12 a Select SERDES Mode in the Operation Mode dropdown list b Select ADF4372 from the DAC Cloc...

Page 14: ...eld to the desired shift frequency in Hz 7 Change the DC Back Off dB box to 0 dB This step causes the fundamental tone at 800 MHz to shift by the amount determined in the Frequency Shift field 8 Click...

Page 15: ...interpolation is equal to 1 the DPGDownloader software displays a single tone in the Vector dropdown box as shown in Figure 15 The data type is real only not complex and Interpolation Mode is set to...

Page 16: ...k Source dropdown box see Figure 4 To simplify configuration and avoid entering commands manually into the register map one at a time an ACE macro can be used to play a sequence ACE macros can play a...

Page 17: ...ol them and set bits whereas in the Registers view the control is by bit or hexadecimal word Both views can program the registers and are based on user preference Because the AD9166 has a large regist...

Page 18: ...Lane 5 on the AD9166 Lane 5 of the Xilinx JESD204B IP Physical Lane 5 on the FMC connector DP5_C2M is Lane 7 on the AD9166 Lane 7 of the Xilinx JESD204B IP Physical Lane 6 on the FMC connector DP6_C2...

Page 19: ...as it is connected across the FMC connector to a carrier board that supports the VITA 57 x standard When using the ADS7 V2EBZ connect the evaluation board to its FMC connector With a USB cable connect...

Page 20: ...n board provides SYSREF only when it is configured for Subclass 1 with SYSREF generated by the HMC7044 SYSREF cannot be provided to the ADS7 V2EBZ externally through an SMA connector on the evaluation...

Page 21: ...AD9166 FMC EBZ User Guide UG 1698 Rev 0 Page 21 of 23 22324 022 Figure 22 Register Write Error Indicating ACE Does Not Recognize the Evaluation Board...

Page 22: ...good practice to use the latest version of DPGDownloader and upload the latest firmware version to the ADS7 V2EBZ To manually update the ADS7 V2EBZ firmware open the DPGDownloader application and clic...

Page 23: ...r party for any reason Upon discontinuation of use of the Evaluation Board or termination of this Agreement Customer agrees to promptly return the Evaluation Board to ADI ADDITIONAL RESTRICTIONS Custo...

Reviews: