Analog Devices AD9166-FMC-EBZ, User Manual

Page: 4 / 23

UG-1698 AD9166-FMC-EBZ User Guide
Rev. 0 | Page 4 of 23
EXTERNAL CLOCKING
Nearly all the clocks that can be generated on the AD9166-
FMC-EBZ evaluation board can be provided from external
sources as well, using the J1, J4, and J61 SMA ports. One
exception is the SYSREF± clock, which can be provided
externally directly to the
AD9166 , through the FMC connector.
The J1 SMA port allows connecting a bit rate/40 clock to the
FMC connector and downstream FPGA. The J4 SMA port
allows connecting an external DAC clock. The J61 SMA port
allows connecting an external reference to PLL1 of the
HMC7044 to lock the on-board VCXO.
Various clocking schemes exist, using either on-board clocking
or external clock sources, or both.
COMMON CLOCKING SCHEMES
The following four basic clocking schemes cover typical
applications encountered by end users:

All internal clocking with the option to lock the clock tree
to an external reference connected to J61.

All external clocking with an external DAC clock connected
to J4 and an external bit rate/40 clock connected to J1.
SYSREF± can be provided across the FMC connector from
an FPGA development kit. The
ADS7-V2EBZ cannot be
configured to generate an external SYSREF± signal to the
FMC connector.

External DAC clock connected to J4 with a low frequency
external reference connected to J61. The reference is then
routed to PLL1 to lock the VCXO, and the VCXO is used
as a reference to PLL2 of the
HMC7044 to generate the bit
rate/40 clock and both SYSREF± clocks to the AD9166 and
ADS7-V2EBZ .

External DAC clock connected to J4, from which a high
frequency external reference is derived and connected to
J61. The reference is then routed to the FIN path of the
HMC7044 to generate the bit rate/40 clock and both
SYSREF± clocks to the AD9166 and ADS7-V2EBZ .
Typically, the input to J4 and J61 is optimally derived from
a single clock source across a splitter.
Other less common schemes can be supported, and the end
user is encouraged to customize the evaluation board as needed
for evaluation.
AD9166
DAC
SERDES JESD204B
AMP
RF OUTPUT
12VIN GND1
CLOCK INPUT
EXTERNAL REFERENCE
FPGA
EXTERNAL REFERENCE
HMC7044
ADF4372
FPGA
REFERENCE
CLOCK
(LANE RATE/40)
SPI
FIN
OSCIN
CPOUTx
RF8x
REF
IN
122.88MHz
VCXO
NOTES
1. ALL SWITCHES ARE 0Ω RESISTORS (SOLDER JUMPERS).
2. REF
IN
IS THE REFERENCE INPUT.
3. FIN IS THE EXTERNAL VCO INPUT ON THE CLKIN1/FIN PIN.
RFAUX8x
REF
IN
J4
J32
J61 J1
22
32
4-
00
2
SYSREF±
SYSR
EF
±
CL
K±
Figure 3. Block Diagram of the AD9166-FMC-EBZ Evaluation Board