UG-1698
Rev. 0 | Page 13 of 23
CONFIGURE THE EVALUATION BOARD
After configuring the FPGA board (
), configure
the AD9166-FMC-EBZ evaluation board using the hardware.
Perform the following steps:
1.
Open the
software from
Start
>
Programs
>
Analog
Devices
>
ACE)
. A window appears similar to Figure 5.
2.
Open the evaluation board view by double clicking the
AD9166-FMC-EBZ evaluation board icon, as shown in
Figure 5.
3.
Using the
AD9166 STARTUP WIZARD
on the left side of
the window, follow these steps, as shown in Figure 12:
a.
Select
SERDES Mode
in the
Operation Mode
dropdown list.
b.
Select
ADF4372
from the
DAC Clock Source
dropdown box in the
AD9166 STARTUP WIZARD
c.
Set
FDAC
to 4.9152 GHz.
d.
Set
Interpolation
to 1.
e.
Set
Serdes Lanes
to 8. Note that 8 is the only
supported lane number for 1× interpolation (bypass)
mode. The minimum interpolation ratio is 1 for the
f.
Click the
Apply
button at the bottom of the
AD9166
STARTUP WIZARD
window.
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4-
01
2
Figure 12. AD9166-FMC-EBZ Evaluation Board View and Clock Source Selection in
