manualshive.com logo in svg

AMD -K6-2/450 - MHz Processor, Application Note

Share
Download
AMD -K6-2/450 - MHz Processor Application Note Download Page 31

Model 7 and Model 8/[7:0] Registers

19

23913A/0—November 2000

Embedded AMD-K6™ Processors BIOS Design Guide

Preliminary Information

Write Handling Control Register (WHCR)

The Write Handling Control Register (WHCR) (see Figure 3 on
page 20) is an MSR that contains three fields — the Write
Cacheability Detection Enable (WCDE) bit, the Write Allocate
Enable Limit (WAELIM) field, and the Write Allocate Enable
15-to-16-Mbyte (WAE15M) bit. The WHCR register is MSR
C000_0082h.

AMD-K6 processors contain a split level-1 (L1) 64-Kbyte
writeback cache organized as a separate 32-Kbyte instruction
cache and a 32-Kbyte data cache with two-way set associativity.
The cache line size is 32 bytes and lines are read from memory
using an efficient pipelined burs t re ad cy cle. Further
performance gains are achieved by the implementation of a
write allocation scheme.

Write Allocation

A write allocate, if enabled, occurs when the processor has a
pending memory write cycle to a cacheable line and the line
does not currently reside in the L1 cache. For more information,
see the Implementation of Write Allocate in the K86™ Processors
Application Note, order# 21326, and the “Cache Organization”
chapter in the appropriate AMD-K6 or AMD-K6E processor
data sheet.

This section describes two programmable mechanisms used by
the processor to determine when to perform write allocate.
When either of these mechanisms indicates that a pending
write is to a cacheable area of memory, a write allocate is
performed.

B e fo re   e n a b l i n g   w r i t e   a l l o c a t e   o r   c h a n g i n g   m e m o ry
cacheability/writeability, the BIOS must writeback and
invalidate the internal cache by using the WBINVD instruction.
In addition, write allocate should be enabled only after
performing any memory sizing or typing algorithms.

Summary of Contents for -K6-2/450 - MHz Processor

Page 1: ... Embedded AMD K6 Processors BIOS Design Guide Publication 23913 Rev A Amendment 0 Issue Date November 2000 Application Note ...

Page 2: ...ime without notice No license whether express implied arising by estoppel or otherwise to any intellectual property rights is granted by this publication Except as set forth in AMD s Standard Terms and Conditions of Sale AMD assumes no liability whatsoever and disclaims any express or implied warranty relating to its products including but not limited to the implied warranty of merchantability fit...

Page 3: ...6 CPUID 6 CPU Speed Detection 6 Model Specific Registers MSRs 6 Cache Testing 7 SMM Issues 7 States after RESET and INIT 8 Register States after RESET and INIT 8 Processor State after INIT 9 Built In Self Test BIST 10 CPUID Identification Algorithms 11 System Management Mode SMM 13 State Save Map Differences 13 I O Trap Dword Differences 13 Model Specific Registers Overview 14 Standard Model Speci...

Page 4: ...Access Register L2AAR 48 Enhanced Power Management Register EPMR Low Power Versions 54 EPM 16 Byte I O Block Low Power Versions Only 55 Embedded AMD Processor Recognition 57 CPUID Instruction Overview 57 Testing for the CPUID Instruction 58 Using CPUID Functions 59 Identifying the Processor s Vendor 60 Testing For Extended Functions 61 Determining the Processor Signature 61 Identifying Supported F...

Page 5: ...formation Software Timing Dependencies Relative to Memory Controller Setup 69 Pipelining Support 69 Read Only Memory 70 Appendix A 71 CPUID 71 Standard Functions 72 Extended Functions 75 Cache Associativity Field Definitions 80 Appendix B 81 Values Returned by the CPUID Instruction 81 Index 83 ...

Page 6: ...vi Contents Embedded AMD K6 Processors BIOS Design Guide 23913A 0 November 2000 Preliminary Information ...

Page 7: ...ty Control Register UWCCR Models 8 F 8 9 and D 31 Figure 8 Processor State Observability Register PSOR Models 8 F 8 9 and Standard Power D 34 Figure 9 Page Flush Invalidate Register PFIR Models 8 F 8 9 and D 36 Figure 10 Extended Feature Enable Register EFER Models 9 and D 39 Figure 11 L2 Cache Organization AMD K6 III Processor 40 Figure 12 L2 Cache Sector and Line Organization 41 Figure 13 L2 Tag...

Page 8: ... 23 L2 Tag Information AMD K6 2E Processor EAX 52 Figure 24 L2 Tag Information AMD K6 IIIE Processor EAX 52 Figure 25 LRU Byte same as Figure 16 53 Figure 26 Enhanced Power Management Register EPMR Low Power Model D 54 Figure 27 EPM 16 Byte I O Block Low Power Model D 55 Figure 28 Bus Divisor and Voltage ID Control BVC Field Low Power Model D 56 Figure 29 Contents of EAX Register Returned by Funct...

Page 9: ...t Offset FFA4h 13 Table 7 Summary by Register of MSR Differences within the AMD K6 Family 14 Table 8 Summary by Model of MSR Differences within the AMD K6 Family 15 Table 9 Model Specific Registers Supported by Models 7 and 8 7 0 17 Table 10 Extended Feature Enable Register EFER Definition Models 7 and 8 7 0 18 Table 11 SYSCALL SYSRET Target Address Register STAR Definition Models 8 9 and D 22 Tab...

Page 10: ... Power Model D 54 Table 26 EPM 16 Byte I O Block Definition Low Power Model D 55 Table 27 Bus Divisor and Voltage ID Control BVC Definition Low Power Model D 56 Table 28 CPUID Functions in AMD K6 Processors 60 Table 29 Processor Signatures for AMD K6 Processors 62 Table 30 Standard and Extended Feature Bits 63 Table 31 Standard Feature Flag Descriptions 74 Table 32 Extended Feature Flag Descriptio...

Page 11: ...Revision History xi 23913A 0 November 2000 Embedded AMD K6 Processors BIOS Design Guide Preliminary Information Revision History Date Rev Description November 2000 A Initial public release ...

Page 12: ...xii Revision History Embedded AMD K6 Processors BIOS Design Guide 23913A 0 November 2000 Preliminary Information ...

Page 13: ...lowing processors in the AMD K6 family AMD K6E embedded processor AMD K6 2 processor AMD K6 2E embedded processor AMD K6 2E embedded processor AMD K6 III processor AMD K6 IIIE embedded processor There can be more than one way to implement the functionality detailed in this document and the information provided is for demonstration purposes All referenced AMD K6 processor documents can be found on ...

Page 14: ...ences between the models and steppings of the AMD K6 family of processors Table 1 Features of the AMD K6 Processor Family Processor Model Stepping Process in microns Number of MSRs1 Notes 1 Refer to Model Specific Registers Overview on page 14 for more information 3DNow Instructions 3DNow Extensions AMD PowerNow Technology L2 Cache AMD K6E 7 0 25 6 AMD K6 2 8 7 0 0 25 7 Yes AMD K6 2 and AMD K6 2E ...

Page 15: ...factured in the 0 25 micron process and was the original version of the AMD K6 2 available as a desktop product Model 8 7 0 implements the same six MSRs as the Model 7 and the bits and fields within these six MSRs are defined identically Model 8 7 0 also implements the SYSCALL SYSRET Target Address Register STAR MSR for a total of seven MSRs Model 8 F 8 Model 8 F 8 is any of eight possible model s...

Page 16: ...orting the 3DNow instruction set and a 100 MHz processor bus the AMD K6 2E processor contains a 128 Kbyte backside L2 cache It also supports the 3DNow DSP instructions extensions Low power versions of the processor support AMD PowerNow technology Model D 7 4 Model D 7 4 is any of four possible model steppings models D 4 D 5 D 6 or D 7 Model D 7 4 is manufactured in the 0 18 micron process Model D ...

Page 17: ...ition to supporting the 3DNow instruction set and a 100 MHz processor bus the AMD K6 IIIE processor contains a 256 Kbyte backside L2 cache It also supports the 3DNow DSP instruction extensions Low power versions of the processor support AMD PowerNow technology Model D 3 0 Model D 3 0 is any of four possible model steppings models D 0 D 1 D 2 or D 3 Model D 3 0 is manufactured in the 0 18 micron pr...

Page 18: ...mpare the result to the real time clock RTC to determine the operating frequency See the CPU Speed Determination Program available on the AMD website at http www amd com products cpg bin Display the recommended BIOS boot string as shown in Table 5 on page 11 Model Specific Registers MSRs Only access MSRs implemented in the processor Enable write allocation by programming the Write Handling Control...

Page 19: ...do contain an MSR that allows for testing of their L2 caches This MSR is called L2AAR and it is described in Level 2 Cache Array Access Register L2AAR on page 40 SMM Issues The System Management Mode SMM functionality of the processor is the same as the Pentium processor Implement the processor SMM state save area in a similar manner as Pentium processors except for the IDT Base and possibly Penti...

Page 20: ...SET Register RESET State EDX 0000_05MSh1 Notes 1 M represents the Model and S represents the Stepping EFER 0000_0000_0000_0000h STAR2 2 Processor Model 7 does not support the STAR register 0000_0000_0000_0000h WHCR 0000_0000_0000_0000h Table 3 AMD K6 Processor Model 8 F 8 and AMD K6 2E Processor Model 8 F 8 State after RESET Register RESET State EDX 0000_05MSh1 Notes 1 M represents the Model and S...

Page 21: ...sets any pending NMI interrupt upon sampling INIT asserted INIT can be used as an accelerator for 80286 code that requires a reset to exit from protected mode back to real mode Table 4 AMD K6 2E Model D AMD K6 III Model 9 and AMD K6 IIIE Processors Model D State after RESET Register RESET State EDX 0000_05MSh1 Notes 1 M represents the Model and S represents the Stepping EFER2 2 Because EFER 4 equa...

Page 22: ...lly following the falling transition of RESET The results of the test are contained in the general purpose register EAX If EAX contains 0000_0000h then BIST was successful If the contents of EAX are non zero the BIST failed The internal resources tested during BIST include the following L1 instruction and data caches L2 unified cache models 9 and D only Instruction and data translation lookaside b...

Page 23: ...be displayed for AMD K6 processors are shown in Table 5 For example a BIOS boot string for a Model 9 stepping 3 450 MHz AMD K6 III processor would look like this AMD K6 tm III 450 Figure 1 on page 12 shows a flow chart for the CPUID instruction Use this chart to implement a CPUID algorithm Table 5 Recommended Boot Strings for AMD K6 Processors Model Recommended Boot String Display1 Notes 1 The val...

Page 24: ...ction EAX 8000_0001h Utilize Vendor String and Extended Function Feature bits to determine 3DNow 3DNow Extensions and MMX Extensions support Execute CPUID Extended Functions EAX 8000_0002h 8000_0003h and 8000_0004h to display processor name string Execute CPUID Extended Functions EAX 8000_0005h and EAX 8000_0006h Model 9 Model D to gather processor cache and TLB information Done Tune software to o...

Page 25: ...emented in the Pentium processor in one way The Interrupt Descriptor Table IDT base location in the AMD K6 processors is located at offset FF90h The Pentium processor has the IDT base located at offset FF94h I O Trap Dword Differences The I O trap dword is located at offset FFA4h Its AMD K6 processor bit fields are shown in Table 6 This state save area which is reserved in Pentium processors conta...

Page 26: ...e AMD K6 Family Register Mnemonic ECX Value Models Description Machine Check Address Register MCAR 00h All page 16 Machine Check Type Register MCTR 01h All page 16 Test Register 12 TR12 0Eh All page 16 Time Stamp Counter TSC 10h All page 16 Extended Feature Enable Register EFER C000_0080h 7 8 7 0 page 18 8 F 8 page 24 9 D page 39 Write Handling Control Register WHCR C000_0082h 7 8 7 0 page 19 8 F ...

Page 27: ...BF VID EBF 7 All X X X 8 7 0 X X X X 8 F 8 X X X X X X X X X 9 3 0 X X X X X X X X X X X D 3 0 7 4 X X X X X X X X X4 X5 X X X5 Notes 1 There are four MSRs that every model and stepping of the AMD K6 family of processors support identically MCAR MCTR TR12 and TSC 2 L2D EWBEC and DPE are bits fields supported in EFER for the indicated models steppings All models steppings support the System Call Ex...

Page 28: ...E bit in Control Register 4 CR4 bit 6 as a read write bit However the state of this bit has no effect on the operation of the processor Test Register 12 TR12 The processor provides the 64 bit Test Register 12 TR12 but only the Cache Inhibit CI bit bit 3 of TR12 is supported All other bits in TR12 have no effect on the processor s operation Note The I O Trap Restart function bit 9 of TR12 is always...

Page 29: ...able 9 Model Specific Registers Supported by Models 7 and 8 7 0 Register Name Mnemonic ECX Value Description Comments Machine Check Address Register MCAR 00h page 16 Identical on all models Machine Check Type Register MCTR 01h page 16 Identical on all models Test Register 12 TR12 0Eh page 16 Identical on all models Time Stamp Counter TSC 10h page 16 Identical on all models Extended Feature Enable ...

Page 30: ...ister EFER Models 7 and 8 7 0 1 0 63 S C E Reserved Symbol Description Bit SCE System Call Extension 0 Table 10 Extended Feature Enable Register EFER Definition Models 7 and 8 7 0 Bit Description R W Function 63 1 Reserved R Writing a 1 to any reserved bit causes a general protection fault to occur All reserved bits are always read as 0 0 System Call Extension SCE 1 Notes 1 The AMD K6E processor M...

Page 31: ...ns are achieved by the implementation of a write allocation scheme Write Allocation A write allocate if enabled occurs when the processor has a pending memory write cycle to a cacheable line and the line does not currently reside in the L1 cache For more information see the Implementation of Write Allocate in the K86 Processors Application Note order 21326 and the Cache Organization chapter in the...

Page 32: ...rite cycle is cacheable by means of one of the other write allocate mechanisms Write to a Cacheable Page and Write to a Sector for more information see the Cache Organization chapter in the appropriate AMD K6 or AMD K6E processor data sheet The maximum value of this limit is 27 1 4 Mbytes 508 Mbytes When all the bits in this field are set to 0 all memory is above this limit and the write allocate ...

Page 33: ...l number of uncommon memory mapped I O adapters that use this particular memory address space If the system contains one of these peripherals the bit should be set to 0 even if the WAE15M bit is set to 0 write allocates can still occur between 15 Mbytes and 16 Mbytes due to the Write to a Cacheable Page and Write to a Sector mechanisms The WAE15M bit is ignored if the value in the WAELIM field is ...

Page 34: ...on Application Note order 21086 Figure 4 SYSCALL SYSRET Target Address Register STAR Models 8 9 and D Table 11 SYSCALL SYSRET Target Address Register STAR Definition Models 8 9 and D Bit Description R W Function 63 48 SYSRET CS and SS Selector Base R W During the SYSRET instruction this field is copied into the CS register and the contents of this field plus 1000b are copied into the SS register 4...

Page 35: ...ical on all models Machine Check Type Register MCTR 01h page 16 Identical on all models Test Register 12 TR12 0Eh page 16 Identical on all models Time Stamp Counter TSC 10h page 16 Identical on all models Extended Feature Enable Register EFER C000_0080h page 24 Newly defined for Model 8 F 8 Write Handling Control Register WHCR C000_0082h page 27 Newly defined for Model 8 F 8 SYSCALL SYSRET Target ...

Page 36: ...cles into this merge buffer The merge Table 13 Extended Feature Enable Register EFER Definition Model 8 F 8 Bit Description R W Function 63 4 Reserved R Writing a 1 to any reserved bit causes a general protection fault to occur All reserved bits are always read as 0 3 2 EWBE Control EWBEC R W This 2 bit field controls the behavior of the processor with respect to the ordering of write cycles and t...

Page 37: ...ing that a subsequent write cycle that hits the cache does not complete ahead of the external write cycle However the addition of the write merge buffer introduces the potential for out of order write cycles to occur between writes to the merge buffer and writes to the processor s cache Because these writes occur entirely within the processor and are not sent out to the processor bus the system lo...

Page 38: ...ed If EWBE is sampled negated the processor delays the commitment of write cycles to processor cache lines in the modified state or exclusive state until EWBE is sampled asserted This setting is the default after RESET and provides the lowest performance of the three settings because full write ordering is maintained Write Ordering and Performance Table 14 summarizes the three settings of the EWBE...

Page 39: ... using an efficient pipelined burst read cycle Further performance gains are achieved by the implementation of a write allocation scheme Write Allocation A write allocate if enabled occurs when the processor has a pending memory write cycle to a cacheable line and the line does not currently reside in the L1 cache For more information on write allocate see the Implementation of Write Allocate in t...

Page 40: ... more information see the Cache Organization chapter in the appropriate AMD K6 or AMD K6E processor data sheet The maximum value of this limit is 210 1 4 Mbytes 4092 Mbytes When all the bits in this field are set to 0 all memory is above this limit and the write allocate mechanism is disabled even if all bits in the WAELIM field are set to 0 write allocates can still occur due to the Write to a Ca...

Page 41: ...one of these peripherals the bit should be set to 0 even if the WAE15M bit is set to 0 write allocates can still occur between 15 Mbytes and 16 Mbytes due to the Write to a Cacheable Page and Write to a Sector mechanisms The WAE15M bit is ignored if the value in the WAELIM field is set to less than 16 Mbytes By definition write allocations are not performed in the memory area between 640 Kbytes an...

Page 42: ... multiple write cycles into a single write cycle reduces processor bus utilization and processor stalls thereby increasing the overall system performance This memory type is applicable for linear video frame buffers Note The MTRRs defined in this document are not software compatible to the MTRRs defined by the Pentium Pro and Pentium II processors The programmer accesses the MTRRs by addressing th...

Page 43: ...AND operations are equal then the generated physical address is considered within the range That is if Mask Physical Base Address Mask Physical Address Generated then the physical address generated by the processor is in the range WCn n 0 1 When set to 1 this memory range is defined as write combinable refer to Table 15 Write combinable memory is uncacheable UCn n 0 1 When set to 1 this memory ran...

Page 44: ...ask must be contiguous Likewise all bits set to 0 in the physical address mask must be contiguous For example 111_1111_1100_0000b is a valid physical address mask 111_1111_1101_0000b is invalid Table 16 lists the valid physical address masks and the resulting range sizes that can be programmed in the UWCCR register Table 16 Valid Masks and Range Sizes for UWCCR Register Masks Size 111_1111_1111_11...

Page 45: ...ields a physical base address 0 field of 000_0000_1000_0000b Because the uncacheable range size is 16 Mbytes the physical mask value 0 field is 111_1111_1000_0000b according to Table 16 on page 32 Bit 1 of the UWCCR register WC0 is set to 0 and bit 0 of the UWCCR register is set to 1 UC0 Extracting the 15 most significant bits of the 32 bit physical base address that corresponds to 1 Gbyte 4000_00...

Page 46: ...set to 0 for Models 9 and D STEP Field This read only field contains the stepping ID This is identical to the value returned by the CPUID standard function 1 in EAX 3 0 BF Field This read only field contains the value of the BF signals sampled by the processor during the falling transition of RESET which allows the BIOS to determine the frequency of the host bus The core frequency must first be kn...

Page 47: ...0b 6 0x1 Notes 1 The 2 0x ratio that is supported on models 7 and 8 7 0 is not supported on models 8 F 8 or 9 Instead if BF 2 0 equals 110b a ratio of 6 0x is selected 111b 3 5x 000b 4 5x 001b 5 0x 010b 4 0x 011b 5 5x State of BF 2 0 Processor Clock to Bus Clock Ratio 100b 2 0x1 Notes 1 The 2 5x ratio that is supported on model 8 F 8 and 9 is not supported on standard power model D Instead if BF 2...

Page 48: ...s 9 and D Figure 9 Page Flush Invalidate Register PFIR Models 8 F 8 9 and D LINPAGE Field This 20 bit field must be written with bits 31 12 of the linear address of the 4 Kbyte page that is to be invalidated and optionally flushed from the L1 cache PF Bit If an attempt to invalidate or flush a page results in a page fault the processor sets the PF bit to 1 and the invalidate or flush operation is ...

Page 49: ...rs to the specified linear page If a 0 is written to this bit the operation is a flush in which case all cache lines in the modified state within the specified page are written back to memory after which the entire page is invalidated If a 1 is written to this bit the operation is an invalidation in which case the entire page is invalidated without the occurrence of any writebacks ...

Page 50: ...ported by Model 9 Register Name Mnemonic ECX Value Description Comments Machine Check Address Register MCAR 00h page 16 Identical on all models Machine Check Type Register MCTR 01h page 16 Identical on all models Test Register 12 TR12 0Eh page 16 Identical on all models Time Stamp Counter TSC 10h page 16 Identical on all models Extended Feature Enable Register EFER C000_0080h page 39 Adds L2 Disab...

Page 51: ...1 to any reserved bit causes a general protection fault to occur All reserved bits are always read as 0 4 L2 Disable L2D R W If L2D is set to 1 the L2 cache is completely disabled This bit is provided for debug and testing purposes For normal operation and maximum performance this bit must be set to 0 this is the default setting following reset 3 2 EWBE Control EWBEC R W This 2 bit field controls ...

Page 52: ... recently used LRU information Figure 11 L2 Cache Organization AMD K6 III Processor The L2AAR register is MSR C000_0089h The operation that is performed on the L2 cache is a function of the instruction executed RDMSR or WRMSR and the contents of the EDX register The EDX register specifies the location of the access and whether the access is to the L2 cache data or tags see Figure 13 on page 41 Fig...

Page 53: ...and the T D bit Figure 13 L2 Tag or Data Location AMD K6 III Processor EDX Upper Dword Lower Dword Octet 0 Line 1 Octet 1 Octet 2 Octet 3 Upper Dword Lower Dword Line 0 Sector Reserved 0 Set 21 31 20 19 17 16 5 15 18 Way 4 3 2 1 6 Symbol Description Bit Set Selects the desired cache set 15 6 Line Selects Line1 1 or Line0 0 5 Octet Selects one of four octets 4 3 Dword Selects upper 1 or lower 0 dwo...

Page 54: ...g the cache data the result is placed in EAX in the format as illustrated in Figure 15 on page 43 Similarly if the L2 tag is written the write data is taken from EAX When accessing the L2 tag the Line Octet and Dword fields of the EDX register are ignored Table 21 Tag versus Data Selector Instruction T D EDX 20 Operation RDMSR 0 Read dword from L2 data array into EAX Dword location is specified by...

Page 55: ...egister EAX 15 The length of the L2 tag required to support the 256 Kbyte L2 cache on the AMD K6 III processor is 16 bits which corresponds to bits 31 16 of the EAX register However the AMD K6 III processor provides a total of 17 bits for storing the L2 tag that is 16 bits for the tag EAX 31 16 plus an additional bit for internal purposes EAX 15 During normal operation the AMD K6 III processor ens...

Page 56: ... the tag is being written that is EAX 15 must be equal to EDX 15 refer to Figure 13 on page 41 and Figure 15 on page 43 It is important to note that this special consideration is only required if the AMD K6 III processor will subsequently be expected to properly execute instructions or access data from the L2 cache following the setup of the L2 cache by means of the L2AAR register If the intent of...

Page 57: ...achine Check Address Register MCAR 00h page 16 Identical on all models Machine Check Type Register MCTR 01h page 16 Identical on all models Test Register 12 TR12 0Eh page 16 Identical on all models Time Stamp Counter TSC 10h page 16 Identical on all models Extended Feature Enable Register EFER C000_0080h page 39 Adds L2 Disable bit L2D to Model 8 F 8 implementation Write Handling Control Register ...

Page 58: ...or during the falling transition of RESET Note This BF divisor value may be different than the BF divisor value supplied to the processor s internal PLL VID Field This read only field contains the Voltage ID bits driven to the processor VID 4 0 pins at RESET These bits are initialized to 01010b and driven on the VID 4 0 pins at RESET Note Low power AMD K6 2E and AMD K6 IIIE processors support AMD ...

Page 59: ... allows the BIOS to determine the frequency of the host bus The core frequency must first be determined using the Time Stamp Counter method See Time Stamp Counter TSC on page 16 The core frequency is then divided by the processor to bus clock ratio as determined by the EBF field of the PSOR register see Table 23 The result is the frequency of the processor bus Table 23 Processor to Bus Clock Ratio...

Page 60: ... 18 Four 32 Kbyte ways AMD K6 2E processor or four 64 Kbyte ways AMD K6 IIIE processor Each way contains 512 AMD K6 2E processor or 1024 AMD K6 IIIE processor sets Each set contains four 64 byte sectors one sector in each way Each sector contains two 32 byte cache lines Each cache line contains four 8 byte octets Each octet contains an upper and lower dword 4 bytes Each line within a sector contai...

Page 61: ...E processor and Figure 21 for the AMD K6 IIIE processor of the address of a cache line equals 1 then this cache line is stored in Line 1 of a sector Similarly if bit 5 of the address of a cache line equals 0 then this cache line is stored in Line 0 of a sector Figure 19 L2 Cache Sector and Line Organization same as Figure 12 Bit 15 of EDX which is the most significant bit of the Set field is not u...

Page 62: ...r Line0 0 5 Octet Selects one of four octets 4 3 Dword Selects upper 1 or lower 0 dword 2 L i n e Octet D w o r d T D Symbol Description Bit T D Selects Tag 1 or Data 0 access 20 Way Selects desired cache way 17 16 14 Reserved 0 Set 21 31 20 19 17 16 5 15 18 Way 4 3 2 1 6 Symbol Description Bit Set Selects the desired cache set 15 6 Line Selects Line1 1 or Line0 0 5 Octet Selects one of four octet...

Page 63: ... is placed in EAX in the format as illustrated in Figure 23 on page 52 AMD K6 2E processor and Figure 24 AMD K6 IIIE processor Similarly if the L2 tag is written the write data is taken from EAX When accessing the L2 tag the Line Octet and Dword fields of the EDX register are ignored Table 24 Tag versus Data Selector same as Table 21 Instruction T D EDX 20 Operation RDMSR 0 Read dword from L2 data...

Page 64: ... the sector is least recently used see Figure 25 on page 53 EAX 7 6 indicate the LRU information for Way 0 EAX 5 4 for Way 1 EAX 3 2 for Way 2 and EAX 1 0 for Way 3 C M D Reserved 0 Tag 31 14 12 10 9 7 8 11 LRU Line0ST Line1ST Symbol Description Bit Tag Tag data read or written 31 14 Line1ST Line 1 state M 11 E 10 S 01 I 00 11 10 Line0ST Line 0 state M 11 E 10 S 01 I 00 9 8 LRU Two bits of LRU for...

Page 65: ...0 addresses sets 0 through 511 and bit 15 equal to 1 addresses sets 512 through 1023 In order to set the full 17 bit L2 tag properly when using the L2AAR register EAX 15 must likewise correspond to the set in which the tag is being written that is EAX 15 must be equal to EDX 15 refer to Figure 21 on page 50 and Figure 24 on page 52 It is important to note that this special consideration is only re...

Page 66: ...ent Register EPMR Definition Low Power Model D Bit Description R W Function1 Notes 1 All bits default to 0 when RESET is asserted 63 16 Reserved R All reserved bits are always read as 0 15 4 I O BASE Address IOBASE R W IOBASE defines a base address for a 16 byte block of I O address space accessible for enabling controlling and monitor ing the EPM features 3 2 Reserved R All reserved bits are alwa...

Page 67: ...igure 28 on page 56 shows the format and Table 27 defines the function of each bit of the BVC field located within the 16 byte I O block Note The EPM Stop Grant state is a low power clock control state entered by writing a non zero value to the SGTC field for altering the core voltage and frequency settings System initiated inquire snoop cycles are not supported and must be prevented during EPM St...

Page 68: ...0 the proces sor VID 4 0 pins are unchanged upon entering the EPM Stop Grant state If VIDC 1 the processor VID 4 0 pins are programmed to the VIDO value upon entering the EPM Stop Grant state BIOS should ini tialize this bit to 1 during the POST routine 9 8 Bus Divisor Control BDC R W This 2 bit field controls the mode of bus divisor control If BDC 1 0 00b the BF 2 0 pins are sampled at the fallin...

Page 69: ... present when it checks the feature bits it can utilize these more powerful extensions for dramatically better performance on new multimedia software See http www amd com products cpg bin for example software and source code to detect processor information CPUID Instruction Overview Software operating at any privilege level can execute the CPUID instruction to identify the processor and its featur...

Page 70: ...ing ways Execute the CPUID instruction and check whether an illegal instruction exception occurs If an exception occurs the processor does not have CPUID support Check if the ID bit bit 21 of the EFLAGS register is writable If the bit is writable that is it can be modified the CPUID instruction is supported The operating system OS environment determines which approach is more appropriate These tec...

Page 71: ...ossible the above code should be preceded by a CLI instruction and followed by an STI instruction which ensures that no interrupts occur between the POPFD and the PUSHFD However traps can still occur even if the code is preceded by a CLI instruction and followed by an STI instruction Using CPUID Functions When software uses the CPUID instruction to identify a processor it is important that it uses...

Page 72: ...MD This string informs the software to follow Table 28 CPUID Functions1 in AMD K6 Processors2 Notes 1 Appendix A on page 71 contains detailed descriptions of the functions 2 Future versions of these processors may implement additional functions Standard Function Extended Function Description AMD K6 E Processor Model 7 AMD K6 2 and AMD K6 2E Processors Model 8 AMD K6 III Processor Model 9 AMD K6 2E...

Page 73: ...ided in the standard feature flags as well as indicators for the additional AMD processor specific feature enhancements The duplication of standard feature bits within the extended feature bits can minimize the number of function calls required by software The exception is bit 11 which indicates that the SYSENTER and SYSEXIT instructions are supported in the standard features and that the SYSCALL ...

Page 74: ...sors Figure 29 Contents of EAX Register Returned by Function 1 Instruction Family 11 8 Model 7 4 Stepping 3 0 12 11 7 3 0 31 Reserved 4 8 Table 29 Processor Signatures for AMD K6 Processors Processor Instruction Family Model Stepping ID1 AMD K6E Processor Model 7 0101b 5h 0111b 7h xxxx AMD K6 2 Processor Model 8 AMD K6 2E Processor Model 8 0101b 5h 1000b 8h xxxx AMD K6 III Processor Model 9 0101b ...

Page 75: ...processor and the RDMSR and WRMSR instructions are supported 1 1 6 PAE Page Address Extensions Page address extensions are supported using an 8 byte directory entry 1 1 7 MCE Machine Check Exception The machine check exception is supported 1 1 8 CMPXCHG8B Instruction The CMPXCHG8B instruction is supported 1 1 9 APIC A local APIC unit is available 1 1 10 Reserved on all AMD processors 0 0 11 SYSENT...

Page 76: ...eriving capabilities from vendor specifiers combined with CPUID model numbers The AMD K6 2E and AMD K6 IIIE processors add a new set of powerful extensions to the x86 instruction set 3DNow extensions See the AMD Extensions to the 3DNow and MMX Instruction Sets Manual order 22466 for more information about these new instructions 23 MMX Instructions The MMX instruction set is supported 1 1 24 FXSAVE...

Page 77: ...dard feature flags in the EDX register MMX Test 4 If bit 23 of the standard feature flags is set to 1 MMX technology is supported MMX instruction support is the basic minimum processor feature required to support other instruction extensions Optional SSE Test 5 Optionally if bit 25 of the standard feature flags is set the processor has streaming single instruction multiple data SIMD extensions SSE...

Page 78: ...r Figure 30 Contents of EAX Register Returned by Extended Function 8000_0001h Displaying the Processor s Name Extended functions 8000_0002h 8000_0003h and 8000_0004h return an ASCII string containing the name of the processor also called the boot string or name string These functions eliminate the need for software to search for the processor name in a lookup table a process requiring a large bloc...

Page 79: ...es and translation lookaside buffer TLB structures The size and organization information is returned in the registers as described in Appendix A on page 71 Software can simply display these values eliminating the need for large pieces of code to test the memory structures Determining AMD PowerNow Technology Information Extended function 8000_0007h provides information regarding the processor s sup...

Page 80: ...III and the AMD K6 IIIE processors implement the following additional instructions 3DNow Instructions 21 new instructions for multimedia software See the 3DNow Technology Manual order 21928 for more information SYSCALL and SYSRET See the SYSCALL and SYSRET Instruction Specification Application Note order 21086 for more information Note that Model 7 processors do not support these instructions The ...

Page 81: ...mory refresh enabled prior to changing memory mode types Refresh should only be enabled after the memory type has been determined Note The BIOS for the K86 family of processors should enable the write allocate mechanisms only after performing any memory sizing or typing algorithms Pipelining Support All production models and steppings of the AMD K6 processor support the WAELIM form of write alloca...

Page 82: ... 9 and D do not support the WCDE bit Read Only Memory The processor s caches must be flushed prior to defining any area of memory as cacheable and read only The BIOS is typically shadowed into main memory and defined as cacheable and read only If the caches are not flushed then a line that resides in the processor s cache that falls within a read only area of memory can be written to which would p...

Page 83: ... processor Model 7 all AMD processors support the CPUID instruction However it is still recommended that software verify that the CPUID instruction is supported See Testing for the CPUID Instruction on page 58 for more information The CPUID instruction supports multiple functions The information associated with each function is obtained by executing the CPUID instruction with the function number i...

Page 84: ...in little endian format AMD processors return a vendor identification string of AuthenticAMD as follows Software uses the vendor identification string as follows To identify the processor as an AMD processor To apply AMD s definition of the CPUID instruction for all additional function calls Function 1 Processor Signature and Standard Feature Flags Input EAX 1 Output EAX Processor Signature EBX Re...

Page 85: ...d in the EDX register and indicate the presence of specific features In most cases a 1 indicates the feature is present and a 0 indicates the feature is not present Table 31 on page 74 contains a list of the currently defined standard feature flags for the AMD K6 family of processors Reserved bits will be used for new features as they are added ...

Page 86: ...del Specific Registers with RDMSR and WRMSR 1 1 1 1 6 PAE Page Address Extensions 0 0 0 0 7 Machine Check Exception 1 1 1 1 8 CMPXCHG8B Instruction 1 1 1 1 9 APIC 0 0 0 0 10 Reserved on all AMD processors 0 0 0 0 11 SYSENTER SYSEXIT 0 0 0 0 12 Memory Type Range Registers 0 0 0 0 13 Global Paging Extension 1 1 1 1 14 Machine Check Architecture 0 0 0 0 15 Conditional Move Instruction 0 0 0 0 16 PAT ...

Page 87: ...ture Flags Function 8000_0001h returns two values the AMD Processor Signature and the Extended Feature Flags The AMD processor signature is returned in the EAX register and identifies the specific processor by providing information regarding its type generation family model and revision stepping The information is formatted as follows EAX 3 0 Stepping ID EAX 7 4 Model EAX 11 8 Generation Family EA...

Page 88: ...Specific Registers with RDMSR and WRMSR 1 1 1 1 6 PAE Page Address Extensions 0 0 0 0 7 Machine Check Exception 1 1 1 1 8 CMPXCHG8B Instruction 1 1 1 1 9 APIC 0 0 0 0 10 Reserved on all AMD processors 0 0 0 0 11 SYSCALL and SYSRET Instructions 1 1 1 1 12 Memory Type Range Registers 0 0 0 0 13 Global Paging Extension 1 1 1 1 14 Machine Check Architecture 0 0 0 0 15 Conditional Move Instruction 0 0 ...

Page 89: ...acter of this group of 16 resides in the most significant byte of EDX The NULL character ASCII 00h is used to indicate the end of the processor name string This feature is useful for processor names that require fewer than 48 characters Note Extended functions 8000_0002h 8000_0003h and 8000_0004h return an incorrect name string for the AMD K6 2E and AMD K6 IIIE processors Model D The returned name...

Page 90: ..._0005h Data TLB Instruction TLB Associativity1 Notes 1 See Associativity for L1 Caches and L1 TLBs on page 80 for more information Entries Associativity1 Entries EBX Bits 31 24 Bits 23 16 Bits 15 8 Bits 7 0 Table 34 ECX Format Returned by Function 8000_0005h L1 Data Cache Size Kbytes Associativity1 Notes 1 See Associativity for L1 Caches and L1 TLBs on page 80 for more information Lines per Tag Li...

Page 91: ... versions of the AMD K6 2E and AMD K6 IIIE processors Model D Input EAX 8000_0007h Output EAX Reserved EBX Reserved ECX Reserved EDX EPM Flags Function 8000_0007h returns information about the processor s AMD PowerNow technology support Table 37 provides the format for the information returned by the 8000_0007h function Table 36 ECX Format Returned by Function 8000_0006h L2 Cache Size Kbytes Assoc...

Page 92: ...ciativity field represents the actual number of ways with a range of 01h through FEh For example a returned value of 02h indicates 2 way associativity and a returned value of 04h indicates 4 way associativity Associativity for L2 Cache The associativity field for the L2 cache is 4 bits wide Table 38 shows the value returned in the associativity field Table 38 Associativity Values for L2 Cache Bits...

Page 93: ... 6874_7541h 444D_4163h 6974_6E65h Function 1 EAX EBX ECX EDX 0000_057Xh Reserved Reserved 0080_01BFh 0000_058Xh Reserved Reserved 0080_21BFh 0000_059Xh Reserved Reserved 0080_21BFh 0000_05DXh Reserved Reserved 0080_21BFh Function 8000_0000h EAX EBX ECX EDX 8000_0005h Reserved Reserved Reserved 8000_0005h Reserved Reserved Reserved 8000_0006h Reserved Reserved Reserved 8000_0007h1 Reserved Reserved...

Page 94: ...defined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Reserved Reserved Reserved 0000_0007h1 Notes 1 Low power versions only Reserved on standard power version 2 Extended functions 8000_0002h 8000_0003h and 8000_0004h each return part of the processor name string Some AMD K6 2E pro cessors may have the following name string function 8...

Page 95: ...sor Control Field 56 Bus Frequency 34 BVC Field 55 BVCM Bit 56 C Cache associativity 80 associativity values for L2 cache table 80 displaying information 67 L2 tag writing 43 53 testing 7 Cache Inhibit Bit 16 CD Bit 9 CI Bit 16 CLI Instruction 59 CMOV Instruction 63 CMPXCHG8B Instruction 63 CPUID Instruction 2 6 65 71 EFLAGS ID bit test 58 flow chart figure 12 functions 59 functions in embedded AM...

Page 96: ... Register L2AAR model 9 40 model D 48 Linear Page Address Field 36 LINPAGE Field 36 LRU Byte figure 43 53 M Machine Check Exception MCE Bit 16 Machine Check Address Register MCAR 16 Machine Check Type Register MCTR 16 Memory DRAM mode changes 69 range restrictions 32 refresh enabling 69 setup subroutines 69 type 30 31 uncacheable UC 30 valid masks and range sizes table 32 write combining WC 30 31 ...

Page 97: ... array access L2AAR 40 48 machine check address MCAR 16 machine check type MCTR 16 page flush invalidate PFIR 36 processor state observability PSOR 34 40 46 states after RESET and INIT 8 SYSCALL SYSRET target address STAR 22 test 12 16 time stamp counter TSC 16 UC WC cacheability control UWCCR 30 write handling control WHCR 19 27 RESET Signal 8 34 RESET State model 8 F 8 8 models 7 and 8 7 0 8 mod...

Page 98: ...minary Information Write Cycles out of order 25 Write Handling Control Register WHCR models 7 and 8 7 0 19 models 8 F 8 9 and D 27 Write Merge Buffer 24 25 Write Combining WC Memory 30 31 WRMSR Instruction 14 16 L2 tag or data selection 42 page flush invalidate register PFIR 36 ...

Reviews:

No comments

Brands by name

Popular brands

Load more brands