ADM-XRC-II User Manual
5.2.2. CCON Register
The CCON register controls access to the ICS9161A clock generator. The
range of frequencies supported is between 25 and 66 MHz. Although the XRC
can operate at frequencies less than 25MHz, the CLKDLL circuits in the
FPGA will not. The maximum frequency of the PCI9656 local bus is 66MHZ.
Refer to the ICS9161A data sheet for further information on determining clock
generator settings.
7 6 5 4 3 2 1 0
CCON MBZ MBZ MBZ MBZ
INTCLK
FEATCLK
DATA/S1
CLK/S0 W
CSTAT RAX RAX RAX
SERERR
INTCLK
FEATCLK
DATA/S1
CLK/S0 R
CLK
Drives clock signal to ICS9161
Determines S0 when static
DATA
Drives data signal to ICS9161
Determines S1 when static
FEATCLK
Do not use
INTCLK
Do not use
The ICS9161 is programmed using CLK and DATA bits to form manchester
encoded sequences. Each sequence consists of a 5 bit unlock preamble
followed by a 24 bit data word all of which must be programmed within 10ms
from the start of the first bit. If programming is not completed within this time,
the ICS9161 will assert SERERR and ignore the remainder of the sequence.
When the ICS9161 is not being programmed, S1 and S0 select the internal
VCLK programming register.
ADM-XRC-II User Manual
Version 1.5
Page 7
