Alpha Data ADM-XRC-II User Manual Download Page 5 | Manualshive

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Alpha Data ADM-XRC-II User Manual Download Page 5

ADM-XRC-II User Manual

1. Introduction

The ADM-XRC-II is a high performance PCI Mezzanine Card (PMC) format
device designed for supporting development of applications using the Virtex-II
series of FPGA’s from Xilinx.

PCI

Interface

PLX 9656

Target/

Initiator

(DMA)

A/D

PCI

Bus

SSRAM

256K x 32/36

XC2V3000-10000

FF1152

Control

Programmable

Clocks

Flash

Memory

Select IO

Front Panel I/O

S
e

l

e
c

t

M

a
p

SSRAM

256K x 32/36

SSRAM

256K x 32/36

SSRAM

256K x 32/46

Pn4 I/O

SSRAM

256K x 32/46

SSRAM

256K x 32/46

1.1. Specifications

The ADM-XRC-II supports high performance PCI operation without the need
to integrate proprietary cores into the FPGA. A PLX PCI9656 provides a rich
set of PCI resources including two high-speed DMA.

Physically conformant to IEEE P1386 Common Mezzanine
Card standard

High performance PCI and DMA controllers

Local bus speeds of up to 66MHz

Six banks of 256k/512kx32/36 ZBT SSRAM

User clock programmable between 0.5MHz and 100MHz

User front panel adapter with up to 146 free IO signals

User rear panel PMC connector with 64 free IO signals

Supports 3.3V and 5V PCI signalling levels (VI/O)

ADM-XRC-II User Manual

Version 1.5

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Summary of Contents for ADM-XRC-II

Page 1: ...ADM XRC II PCI Mezzanine Card User Guide Version 1 5...

Page 2: ...ta Parallel Systems Limited Alpha Data 58 Timber Bush Edinburgh EH6 6QH Scotland UK Phone 44 0 131 555 0303 Fax 44 0 131 555 0728 Email support alphadata co uk Copyright 2002 Alpha Data Parallel Syste...

Page 3: ...ion 9 5 4 Input Clocks 10 5 5 Output Clocks 11 5 6 Local Bus 12 5 7 Synchronous SRAM 13 5 8 Clock pins 13 5 9 User I O Configuration 14 5 9 1 User I O XRM IO34 Front Panel Variant 14 5 9 2 User I O XR...

Page 4: ...ADM XRC II User Manual 11 FPGA Pin Locations 27 ADM XRC II User Manual Version 1 5...

Page 5: ...x 32 46 SSRAM 256K x 32 46 1 1 Specifications The ADM XRC II supports high performance PCI operation without the need to integrate proprietary cores into the FPGA A PLX PCI9656 provides a rich set of...

Page 6: ...e PMC motherboard using M2 5 screws in the four holes provided The PMC bezel through which the I O connector protrudes should be flush with the front panel of the PMC motherboard 2 4 Installing the AD...

Page 7: ...flash SelectMAP and the clock generator In direct slave mode the XRC is a target on the PCI bus for read and write transactions and these are translated into local bus cycles initiated by the PCI9656...

Page 8: ...R2 Local Bus FPGA 1C PCI BAR3 Local Bus Control Flash SelectMap 20 PCI BAR4 Not used 24 PCI BAR5 Not used 28 Card Bus CIS Pointer Not used 2C Subsystem ID Subsystem Vendor ID 30 PCI Base Address for L...

Page 9: ...HOST 4M byte space HOST 4M byte space FPGA 4MB 32 bit space BAR3 S1 BAR2 S0 The PCI9656 can be programmed to support 8 16 or 32 bit local bus widths and this feature is used to match with the device...

Page 10: ...PROG and then releasing it will start the initialisation process The INIT bit is only valid whilst the device is not configured indicated by a zero in DONE After configuration the INIT pin becomes a...

Page 11: ...RAX SERERR INTCLK FEATCLK DATA S1 CLK S0 R CLK Drives clock signal to ICS9161 Determines S0 when static DATA Drives data signal to ICS9161 Determines S1 when static FEATCLK Do not use INTCLK Do not us...

Page 12: ...clear FINT in the ISTAT register depends on the interrupt mode selected by IMODE MODE 0 With edge triggered interrupts writing the FINT bit in ICON clears the corresponding bit in ISTAT For level sen...

Page 13: ...is written with configuration information The mapping of this port is determined by the BREV bit in the MODE register 7 6 5 4 3 2 1 0 SelectMap Configuration Data Byte W NOTE Do not write to the Sele...

Page 14: ...e MCLK signal from the clock generator is the local bus clock used by the FPGA PLX PCI9656 and a support CPLD Both MCLK and VCLK can be programmed between 400kHz and 100MHz A restriction on MCLK is th...

Page 15: ...lock with the local bus clock To do this requires the use of Virtex DCM s that are specifically designed for the purpose of minimising skew between external and internal clock domains The SRAM s are s...

Page 16: ...TRI Burst terminate LREADYIL low OUT TRI Accepts completes data transfer LDREQL 1 0 low OUT Request DMA transfer LDACKL 1 0 low IN DMA transfer acknowledge LEOTL 1 0 low OUT Terminate current DMA tra...

Page 17: ...KE clock enable Where n 0 1 2 3 4 5 Therefore SRAM 0 is controlled by the three bus ports RD0 36 0 RA0 19 0 and RC0 8 0 and these are names used to constrain the pins in the user constraints file or U...

Page 18: ...A link on pins 2 3 selects 2 5V whilst a link on pins 1 2 select 3 3V Each pair of I O signals is routed as shown below FPGA IO CON Rs Rs Rs Rs Rt Rt User 0 User 1 User 2 User 3 The default manufactur...

Page 19: ...1 65 USER 30 32 66 USER 31 33 67 USER 32 CLK All GND 34 68 USER 33 CLK 5 9 2 User I O XRM IO146 Panel Variant Rev2 0 There are 146 I O signals available on the front panel connector and these can be u...

Page 20: ...Single 1 User 35 N a F13 36 Clock 0 ve User 33 H17 37 5V fused 38 Single 2 User 36 N a C16 Pin Function UCF name Term Res V II Pin Pin Function UCF name Term Res V II Pin 39 Data 16 ve User 40 R19 A7...

Page 21: ...5 Data 48 ve User 110 R65 J23 116 Data 49 ve User 112 R61 H22 117 Data 48 ve User 111 J24 118 Data 49 ve User 113 H23 119 Data 50 ve User 114 R68 E27 120 Data 51 ve User 116 R66 C23 121 Data 50 ve Use...

Page 22: ...EARIO 17 17 18 REARIO 16 REARIO 19 19 20 REARIO 18 REARIO 21 21 22 REARIO 20 REARIO 23 23 24 REARIO 22 REARIO 25 25 26 REARIO 24 REARIO 27 27 28 REARIO 26 REARIO 29 29 30 REARIO 28 REARIO 31 31 32 REA...

Page 23: ...rocess DONE should be high If DONE is not high and INIT is set then an error has occurred and will probably be due to an invalid bitstream Note that INIT is not valid when DONE is set as it becomes a...

Page 24: ...ces as well as from the local bus The FPGA can interrupt the host system by asserting the LINTIL active low signal and keeping it asserted until the source of the interrupt is cleared See the ICON reg...

Page 25: ...ing the FPGA from flash on power up or reset and will load the bitstream from the main memory section starting at 0x8001 This is to avoid any problem with the boot block which if locked out cannot be...

Page 26: ...ly during system boot to configure resources requested by the ADM XRC II The main points to note are that the device and vendor ID s are 9656 10B5 and the command register is set for memory and I O ac...

Page 27: ...describes the attributes of Local Bus Space 0 It can be seen that 32 bit local bus width is selected and that ready must be generated by the target space In this case Space 0 is allocated to the FPGA...

Page 28: ...ers and FPGA SelectMAP port Notes 1 Do not enable burst for this region as it may cause side effects that will stop FPGA loading and readback 2 Internal wait states should always be 0 3 Bus width is a...

Page 29: ...transfer codes and general purpose input and output bits Notes 1 A fault with the EEPROM or if the EEPROM is blank will result in the Serial EEPROM Present bit being cleared 2 This register can be us...

Page 30: ...ts There is a utility in the SDK that can be used to view and change the contents of the EEPROM As this device contains PLX PCI9656 initialisation data users must be careful about the changes made ADM...

Page 31: ...ADM XRC II User Manual 11 FPGA Pin Locations Refer to the SDK which contains UCF files for various local bus SRAM and IO configurations ADM XRC II User Manual Version 1 5 Page 27...

Page 32: ...dules Flash Page Info PLX Configuration register info SRAM Clocking Dec 2001 1 2 Updates XRM IO146 Rev 2 0 added Feb 2002 1 3 Updates I O UCF FPGA pin cross reference June 2002 1 4 Updates Reflects Re...

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