ADM-XRC-II User Manual
recommended that alterations to VCLK use REG1 or REG2 to set the new
value so that on reset the VCLK output selects REG0 when S1/S0 are reset.
SRAM
Clocks
Host
Setting
VCLK
MCLK
Virtex
FPGA
CPLD
Control
Logic
PCI9656
ICS
9161A
Osc
14.3181
MHz
5.4. Input
Clocks
There are two primary clock inputs to the FPGA, both from the programmable
clock generator. The VCLK signal from the clock generator is used only by the
FPGA. It is therefore free for use by logic in the FPGA.
The MCLK signal from the clock generator is the local bus clock, used by the
FPGA, PLX PCI9656 and a support CPLD.
Both MCLK and VCLK can be programmed between 400kHz and 100MHz.
A restriction on MCLK is that it must not exceed 66MHz,the maximum
speed of the PCI9656, and should not be lower than 25MHz for reliable
CLKDLL operation
.
MCLK is input to the FPGA on GCK7 (pin AG18) and should be used to drive
a Virtex CLKDLL circuit which aligns the internal FPGA clock to the local bus
clock. The circuit below demonstrates how to align the internal clock of the
FPGA to the local bus clock. The output of the BUFG is available to all flip-
flops in the design.
ADM-XRC-II User Manual
Version 1.5
Page 10