ADM-XRC-II User Manual
5.
ADM-XRC-II Local Bus Architecture
It is useful to refer to the PLX PCI9656 user manual for information on the
operation of the local bus and how address spaces map to the BAR’s in PCI
configuration space. The first two BAR’s decode memory and I/O ranges for
the PCI9656 internal registers.
There are a further two BAR’s (at offsets 0x18 and 0x1C) that map the two
main local bus address spaces, S0 and S1. In the XRC, S0 is an 4Mbyte
memory address space, 32-bits wide and is available for the user to access
the FPGA . S1 maps in a 4Mbyte memory address space, 8 bits wide for
access to the control registers, flash and FPGA SelectMap port.
A00000
800000
SelectMap and
Control
registers
2M x 8 bit
Flash
2M x
8 bit
PCI9656
000000
HOST
4M byte
space
HOST
4M byte
space
FPGA
4MB
32 bit space
BAR3 – S1
BAR2 – S0
The PCI9656 can be programmed to support 8, 16 or 32 bit local bus widths
and this feature is used to match with the device widths fitted on the XRC.
Other than programming the BAR’s with values determined by the host
system, no other programming of the PCI9656 is required in order to access
the local bus registers and devices.
5.1. Characteristics of Address Spaces
The XRC maps two PCI BAR spaces to the local bus and are specified to
operate differently as shown below.
Space
Size Width Burst Prefetch
Burst Term
Local Offset
S0 4MB
32 yes no
yes 0x00000000
S1 4MB 8 yes no
yes 0x00800000
From the PCI side of the PCI9656, transfers to either space may be 8, 16 or
32-bit in width and of any length. The PCI9656 breaks up transfers to suit the
address space on the local bus whilst respecting the characteristics outlined
above.
ADM-XRC-II User Manual
Version 1.5
Page 5
