ADM-XRC-II User Manual
Signal Pin Pin Signal
1 35
USER[0]
2 36
USER[1]
3 37
USER[2]
4 38
USER[3]
5 39
USER[4]
6 40
USER[5]
7 41
USER[6]
8 42
USER[7]
9 42
USER[8]
10 44
USER[9]
11 45
USER[10]
12 46
USER[11]
13 47
USER[12]
14 48
USER[13]
15 49
USER[14]
16 50
USER[15]
17 51
USER[16]
18 52
USER[17]
19 53
USER[18]
20 54
USER[19]
21 55
USER[20]
22 56
USER[21]
23 57
USER[22]
24 58
USER[23]
25 59
USER[24]
26 60
USER[25]
27 61
USER[26]
28 62
USER[27]
29 63
USER[28]
30 64
USER[29]
31 65
USER[30]
32 66
USER[31]
33 67
USER[32]
-CLK
All GND
34 68
USER[33]
-CLK
5.9.2. User I/O XRM IO146 Panel Variant – Rev2.0
There are 146 I/O signals available on the front panel connector and these
can be used individually or in pairs. Each pair of I/O signals is routed as
shown below.
FPGA IO CON
Rs
Rs
Rs
Rs
Rt
Rt
User[0]
User[1]
User[2]
User[3]
The default manufacturing option is Rs=0R and Rt not fitted. Other options are
available. Rs can be used to provide series damping in point to point
applications but for LVDS is 0R. Rt is required for LVDS inputs to provide the
termination voltage from the line current.
ADM-XRC-II User Manual
Version 1.5
Page 15