ADM-XRC-II User Manual
5.2. Local Control Registers
The local bus control registers are implemented in a CPLD attached to the
PCI9656 local bus. The map of these registers is shown below.
S1+offset Write
Read
0 FCON
FSTAT
1 CCON
CSTAT
2 IMSET
IMSTAT
3 IMCLR
IMSTAT
4 ICON
ISTAT
5 PCON
PSTAT
6 MODE
MODE
7 FlashPage
FlashPage
8-15 SelectMap
SelectMap
Registers that are not implemented are marked Must Be Zero (MBZ) and
Read As Don’t Care (RAX). The same applies for bits within implemented
registers that are not used or reserved.
5.2.1. FCON Register
The FPGA can be configured by the host system using the SelectMap port on
the target device. Before this can be achieved, the FPGA must be initialised to
an erased state. Asserting PROG and then releasing it will start the
initialisation process. The INIT bit is only valid whilst the device is not
configured, indicated by a zero in DONE. After configuration, the INIT pin
becomes a user I/O pin and has no further function on the ADM-XRC-II. In
this case the place and route program sets the INIT pin to an input with a
weak pull down thus resulting in INIT appearing set.
7 6 5 4 3 2 1 0
FCON MBZ MBZ MBZ MBZ MBZ MBZ INIT PROG W
FSTAT RAX RAX RAX RAX RAX DONE INIT PROG R
FCON
Function (W0/1 is write value, R is when read)
PROG
W0 - Release PROGRAM to the FPGA
W1 - Asserts PROGRAM pin on the target FPGA
RX - Indicates state of FCON[PROG]
INIT
W0 - Has no effect on FPGA INIT pin
W1 - Asserts INIT pin to FPGA to postpone configuration
R0 - FPGA has no error
R1 - FPGA has asserted INIT
DONE
R0 - FPGA is not configured or is being configured
R1 - FPGA is successfully configured
ADM-XRC-II User Manual
Version 1.5
Page 6
