Alpha Data ADM-XRC-II Pro Hardware Manual Download Page 16

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ADM-

User Manual

ADM-XR-IIPro User Manual

Page 16 of 29

Version 0.2

(Continued)

FPGA

Pin

Signal Connector

Pins Signal FPGA

Pin

D20

IO_73N_1

IO_68N_1

H20

C20

IO_73P_1

IO_68P_1

J20

K17

IO_47N_1

IO_37N_1

F15

L17

IO_47P_1

IO_37P_1

E15

J17

IO_48N_1

IO_38N_1

C15

H17

IO_48P_1

IO_38P_1

C14

H18

IO_55N_1

IO_39P_1

L16

G18

IO_55P_1

IO_39N_1

M16

E17

IO_56P_1

IO_43N_1

K16

E18

IO_56N_1

IO_43P_1

J16

K19

IO_59N_1

IO_44P_1

H16

J19

IO_59P_1

IO_44N_1

G16

H19

IO_60N_1

IO_46N_1

M17

G19

IO_60P_1

IO_46P_1

M18

K21

IO_74P_1

IO_65N_1

C19

J21

IO_74N_1

IO_65P_1

D19

E19

IO_64P_1

IO_37N_0

E28

F19

IO_64N_1

IO_37P_0

F28

G22

IO_75P_0

IO_38N_0

C29

F22

IO_75N_0

100

IO_38P_0

C28

H27

IO_44N_0

101

102

IO_74P_0

J22

G27

IO_44P_0

103

104

IO_74N_0

K22

J27

IO_43N_0

105

106

IO_39N_0

L27

K27

IO_43P_0

107

108

IO_39P_0

M27

D29

IO_85N_0

109

110

IO_67N_1

L20

E29

IO_85P_0

111

112

IO_67P_1

K20

K29

IO_78N_0

113

114

IO_78N_1

L14

L29

IO_78P_0

115

116

IO_78P_1

K14

BB40 MGT_SYS_TXP23

**117

**118

MGT_SYS_RXP23 BB39

BB41 MGT_SYS_TXN23

**119

**120

MGT_SYS_RXN23 BB38

** - Additional MGT channel provided using these pins

FPGA

Pin

Signal Connector

Pins Signal FPGA

Pin

K26

IO_47P_0

121

122

IO_35P_0

C30

L26

IO_47N_0

123

124

IO_35N_0

D30

L24

IO_58N_0

125

126

IO_46P_0

M26

M24

IO_58P_0

127

128

IO_46N_0

M25

E25

IO_56P_0

129

130

IO_48P_0

J26

E26

IO_56N_0

131

132

IO_48N_0

H26

H31

IO_25N_0

133

134

IO_59N_0

J24

J31

IO_25P_0

135

136

IO_59P_0

K24

G33

IO_7P_0

137

138

IO_73N_0

C23

F33

IO_7N_0

139

140

IO_73P_0

D23

E34

IO_2P_0

141

142

IO_60N_0

G24

F34

IO_2N_0

143

144

IO_60P_0

H24

H33

IO_6N_0

145

146

IO_29P_0

K30

J33

IO_6P_0

147

148

IO_29N_0

J30

C32

IO_20P_0

149

150

IO_54N_0

K25

C33

IO_20N_0

151

152

IO_54P_0

L25

H34

IO_1P_0

153

154

IO_64N_0

E24

G34

IO_1N_0

155

156

IO_64P_0

F24

E33

IO_8N_0

157

158

IO_67N_0

K23

D33

IO_8P_0

159

160

IO_67P_0

L23

C24

IO_65P_0

161

162

IO_30N_0

G30

D24

IO_65N_0

163

164

IO_30P_0

H30

E30

IO_34N_0

165

166

IO_55N_0

G25

F30

IO_34P_0

167

168

IO_55P_0

H25

K31

IO_21N_0

169

170

IO_26N_0

G31

L31

IO_21P_0

171

172

IO_26P_0

F31

F26

IO_49N_0

173

174

IO_28N_0

L30

G26

IO_49P_0

175

176

IO_28P_0

M30

E32

IO_19N_0

177

178

IO_68N_0

J23

F32

IO_19P_0

179

180

IO_68P_0

H23

Summary of Contents for ADM-XRC-II Pro

Page 1: ...ADM XR IIPro User Manual Page 1 of 29 Version 0 2 ADM XRC II Pro ADM XP Hardware Manual...

Page 2: ...irport Parkway Suite 470 San Jose CA 95110 USA Phone 408 467 5076 Fax 408 436 5524 Email support alpha data com Copyright 2002 2003 2004 Alpha Data Parallel Systems Ltd All rights reserved This public...

Page 3: ...Revision History Revision Date Comments 0 1 Jul 04 Initial 0 1 DATA1 DATA8 DATA13 and DATA15 polarity swapped DATA38 pin nos swapped in Manual Clock pins updated for XP pinouts were XPL pinouts 0 2 N...

Page 4: ...PGA 10 5 1 CONFIGURATION 10 5 2 CLOCKS 10 5 3 SDRAM DDR MEMORY 12 5 4 DDR2 SSRAM 13 5 5 FLASH MEMORY 14 5 6 POWER SUPPLY 14 6 FRONT PANEL I O 15 6 1 SAMTEC 180 CONNECTOR U8 15 6 2 ROCKETIO MULTI GIGAB...

Page 5: ...and toolkits provided by Xilinx Flexible I O is the key to the ADM XRC II series of boards and the XP is compatible with a wide selection of XRM modules that use the 180 pin Samtec interface 1 1 Speci...

Page 6: ...is powered up The ADM XP must be secured to the PMC motherboard using M2 5 screws in the four holes provided The PMC bezel through which the I O connector protrudes should be flush with the front pan...

Page 7: ...e bridge and the target device The bridge is capable of 66MHz PCI or PCI X operation with 64 bit or 32 bit operation The local bus supports 64 bit at upto 80Mhz The target FPGA is a Virtex II PRO devi...

Page 8: ...DDR DRAM and DDR2 SSRAM devices are clam shelled and appear on both sides of the board J5 Jtag Header J 1 X R M M E Z Z J 2 J 4 JP1 VIO Selection J 3 2V1500 Bridge 2VP70 2VP100 Target ZBT ZBT 1 Flash...

Page 9: ...ignalling Virtex2Pro default 2 5V fast LVCMOS LVTTL lclk AT21 AF1 AF2 AG12 AF7 AD10 AD9 AC10 AC9 Signal Type Purpose lad 0 63 bidir Address and data bus lreset_l unidir Reset to target lads_l bidir In...

Page 10: ...n the bridge and the target device mapped to the PCI bus This enables very rapid download of configuration data controlled by driver and API code in the host The maximum speed that can be achieved is...

Page 11: ...lect 6S J22 IO_74P_0 GCLK6S 0 JP1 select 5P F22 IO_75N_0 GCLK5P 0 JP1 select 4S G22 IO_75P_0 GCLK4S 1 JP1 select 0S K21 IO_74P_1 GCLK0S 1 JP1 select 1P J21 IO_74N_1 GCLK1P 1 JP1 select 2S F21 IO_75P_1...

Page 12: ...s for data and control and SSTL1 for address and clocks Please refer to the UCF for locations of the DDR pins Please note that the FPGA requires the Vref pins to be connected for correct data receptio...

Page 13: ...SRAM Add0 0 21 Dq0 0 31 Bwe0 0 3 Cclk0 Cclkb0 Kclk0 Kclkb0 DDR2 SSRAM Bank1 DDR2 SSRAM Bank 2 DDR2 SSRAM Bank 3 The pins required for each SSRAM controller bank are listed below Name FPGA Pin Type Des...

Page 14: ...O standard be used for the Flash Interface 2VP70 2VP100 FF1704 dq 0 15 RC28F256K3 Strataflash K3 Flash_rst_n ad 0 23 A0 Flash_oe_n Flash_we_n Flash_cs_n VIO Bank 3 4 VCCO 2 5V VCC 2V5 3V3 Flash_wp_n F...

Page 15: ..._8N_1 1 2 IO_35N_1 C13 E10 IO_8P_1 3 4 IO_35P_1 D13 F11 IO_19N_1 5 6 IO_30P_1 H13 E11 IO_19P_1 7 8 IO_30N_1 G13 J10 IO_6N_1 9 10 IO_58N_1 M19 H10 IO_6P_1 11 12 IO_58P_1 L19 G10 IO_7N_1 13 14 IO_54N_1...

Page 16: ...115 116 IO_78P_1 K14 BB40 MGT_SYS_TXP23 117 118 MGT_SYS_RXP23 BB39 BB41 MGT_SYS_TXN23 119 120 MGT_SYS_RXN23 BB38 Additional MGT channel provided using these pins FPGA Pin Signal Connector Pins Signal...

Page 17: ...is given below FPGA Pin Signal Connector Pins Signal FPGA Pin A40 MGT_SYS_TXP2 1 2 MGT_SYS_RXP2 A39 A41 MGT_SYS_TXN2 3 4 MGT_SYS_RXN2 A38 A36 MGT_SYS_TXP3 5 6 MGT_SYS_RXP3 A35 A37 MGT_SYS_TXN3 7 8 MGT...

Page 18: ...V25 AT25 REARIO 19 19 20 REARIO 18 AR25 AN25 REARIO 21 21 22 REARIO 20 AM25 AU26 REARIO 23 23 24 REARIO 22 AT26 AR26 REARIO 25 25 26 REARIO 24 AP26 AM26 REARIO 27 27 28 REARIO 26 AN26 AL25 REARIO 29 2...

Page 19: ...3V3 signalling levels and has the following devices present in the scan chain hdr_TDI Bridge 2V1500 hdr_TMS hdr_TCK hdr_TDO Target 2VP70 2VP100 tck tms The standard XP is configured with the JTAG cha...

Page 20: ...pin Mictor connector This connector is compatible with a wide range of Mictor connectors and is well suited to cabling systems from Precision Interconnect The differential pairs are routed on the XRM...

Page 21: ...rd MII interface suitable for connection to MAC IP in the FPGA A management interface and reset is also provided LEDS are provided on the board and these indicate the following conditions when lit D1...

Page 22: ...63 17 PAIR_9_P 1 D20 61 19 PAIR_9_N 1 F9 24 18 PAIR_10_P 1 E9 22 20 PAIR_10_N 1 L17 67 21 PAIR_11_P 1 K17 65 23 PAIR_11_N 1 C11 30 22 PAIR_12_P 1 C10 32 24 PAIR_12_N 1 J19 83 25 PAIR_13_P 1 K19 81 27...

Page 23: ...PD 0 F22 99 RXD2 O PD 1 D19 92 RXD1 O PD 0 E28 94 RXD0 O PD 0 F28 96 TXEN I 0 C29 98 TXD0 I 0 C28 100 TXD1 I 0 J22 102 TXD2 I 0 K22 104 TXD3 I 0 L27 106 COL O PD 0 K27 107 CRS O PD 1 E13 18 MDC I PU 1...

Page 24: ...st be taken when using these signal pins not to exceed the maximum ratings for the V2PRO device Each pair of I O signals is routed as shown below FPGA IO CON Rs Rs Rs Rs Rt Rt User 0 User 1 User 2 Use...

Page 25: ...23 ve User 54 R26 C14 53 Data 22 ve User 53 J17 54 Data 23 ve User 55 C15 55 Data 24 ve User 56 R29 G18 56 Data 25 ve User 58 R28 L16 57 Data 24 ve User 57 H18 58 Data 25 ve User 59 M16 59 Data 26 ve...

Page 26: ...e User 127 E30 134 Data 57 ve User 129 G25 135 Data 58 ve User 130 R79 L31 136 Data 59 ve User 132 R78 F31 137 Data 58 ve User 131 K31 138 Data 59 ve User 133 G31 139 Data 60 ve User 134 R81 G26 140 D...

Page 27: ...d XRM IO146 allowing termination for LVPECL and BLVDS standards to be implemented on the XRM module rather than externally FPGA IO CON Rs Rs Rs Rs Rt Rt User 0 User 1 User 2 User 3 The default manufac...

Page 28: ...e User 54 R26 C14 53 Data 22 ve User 53 J17 54 Data 23 ve User 55 C15 55 Data 24 ve User 56 R29 G18 56 Data 25 ve User 58 R28 L16 57 Data 24 ve User 57 H18 58 Data 25 ve User 59 M16 59 Data 26 ve User...

Page 29: ...S_TXP15 N a BB8 133 MGT_SYS_RXN15 N a BB6 134 MGT_SYS_TXN15 N a BB9 135 MGT_SYS_RXP14 N a BB3 136 MGT_SYS_TXP14 N a BB4 137 MGT_SYS_RXN14 N a BB2 138 MGT_SYS_TXN14 N a BB5 139 MGT_SYS_RXP3 N a A35 140...

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