Alpha Data ADM-XRC-7V1, User Manual

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ADM-XRC-7V1 User Manual
V1.9 - 23rd Aug 2016
3.6 Configuration
3.6.1 Power-Up Sequence
If valid data is stored in the flash memory, the bridge will automatically configure the Target FPGA at power-up.
This sequence can be inhibited by turning the Flash Boot Inhibit (FBI) switch, SW1-4 to ON. (See Switch
Definitions ).
Note:
If an over-temperature alert is detected from the System Monitor, the target will be cleared by pulsing its
PROG signal. See Automatic Temperature Monitoring .
3.6.2 Bridge-Less Mode
When operating in bridgeless mode, the Target FPGA will be configured directly by a Quad SPI connection to a
1Gb FLASH memory device. This memory device is re-programable over a Xilinx JTAG cable.
This mode is not available in Revision 2 and earlier boards.
Page 14 Functional Description
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