ADM-XRC-7V1 User Manual
V1.9 - 23rd Aug 2016
3.4 Clocks
The ADM-XRC-7V1 provides a wide variety of clocking options. On top of a fixed 200MHz oscillator and clocks
routed from the rear and front panel connectors, the board has 4 user-programmable clocks. These clocks can
be combined with the FPGA's internal PLLs to suit a wide variety of communication protocols.
A complete overview of the clock routing on the ADM-XRC-7V1 is given in
. A description of each clock
follows.
7 Series
MGT/ Banks
MGT111
REFCLK0
REFCLK1
MGT112
REFCLK0
REFCLK1
MGT113
REFCLK0
REFCLK1
MGT114
REFCLK0
REFCLK1
MGT115
REFCLK0
REFCLK1
MGT116
REFCLK0
REFCLK1
MGT117
REFCLK0
REFCLK1
MGT118
REFCLK0
REFCLK1
XMC
P5
XMC
P6
PCIe
REFCLK
Buffer
PCIe
Bridge
200MHZ
Buffer
200MHZ
Source
XRM Interface
User
Programmable
Source
MGT119
REFCLK0
REFCLK1
Note:
REFCLK can be shared with
MGT tiles to the North and South
within a super logic region (SLR in
1500T and 2000T only)
REFCLK
Buffer
250MHZ
Source
DDR3
Banks
19 35
37 39
Bank 14
Figure 5 : Clocks
Note:
Clock Termination
The LVDS clocks do not have termination resistors on the circuit board. On-die terminations in the FPGA must
be enabled by setting the attribute "DIFF_TERM = TRUE". This can either be set in the source code when
instantiating the buffer, or in the User Constraints File (UCF). See the Xilinx Virtex-7 Libraries Guide and
Constraints Guide for further details.
Page 9
Functional Description
ad-ug-1248_v1_9.pdf
