Alpha Data ADM-XRC-7V1 User Manual Download Page 9

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ADM-XRC-7V1 User Manual
V1.9 - 23rd Aug 2016

3.1.1 Switch Definitions

There is a set of eight DIP switches placed on the rear of the board. Their functions are described in

Switch

Definitions

Note:

All switches are OFF by default. Factory Configuration switch must be in the OFF position for normal

operation.

Switch Ref.

Function

ON State

Off State

SW1-1

User Switch to
Target FPGA

SW1-2

Reserved

Normal Operation

SW1-3

Bridge Bypass

Bridge FPGA is bypassed - PCIe lanes
(3:0) are connected directly to the user
FPGA.

Bridge FPGA is used. PCIe lanes (3:0)
are connected to the bridge.

SW1-4

Flash Boot
Inhibit

Target FPGA is not configured from
onboard flash memory.

Target FPGA is configured from on-
board flash memory.

SW1-5

XMC JTAG

Connect JTAG chain to P5

Isolate JTAG chain from P5

SW1-6

E-Fuse

Enable E-Fuse programming voltage
(VccEFuse = 2.5V)

Disable E-Fuse programming voltage
(VccEFuse = 0V)

SW1-7

Factory
Configuration

Normal Operation

SW1-8

Bridge-Less
Mode

Bridge-Less Mode Active - User
bitstream loaded from SPI flash

PCIe Bridge Mode Active - User
bitstream loaded from Bridge

Table 2 : Switch Definitions

Page 5

Functional Description
ad-ug-1248_v1_9.pdf

Summary of Contents for ADM-XRC-7V1

Page 1: ...ADM XRC 7V1 User Manual Document Revision 1 9 23rd Aug 2016...

Page 2: ...form without prior written consent from Alpha Data Parallel Systems Ltd Head Office Address Suite L4A 160 Dundee Street Edinburgh EH11 1DQ UK Telephone 44 131 558 2600 Fax 44 131 558 2700 email sales...

Page 3: ...Voltages 8 3 4 Clocks 9 3 4 1 200MHz Reference Clock REFCLK200M 10 3 4 2 PCIe Reference Clock 0 PCIEREFCLK0 10 3 4 3 PCIe Reference Clock 1 PCIEREFCLK1 10 3 4 4 Programmable Clocks LCLK PROGCLK 0 3 1...

Page 4: ...11 Table 8 MGTCLK_M2C Connections 11 Table 9 XRM_LVDS_CLK Connections 12 Table 10 Voltage and Temperature Monitors 15 Table 11 Temperature Limits 16 Table 12 Status LED Definitions 16 Table 13 Target...

Page 5: ...256MB bank 1GB total 2GB and 4GB option Front panel XRM interface with adjustable voltage 146 GPIO signals and 8 GTX links to user FPGA Rear panel XMC 10 GTX links 38 GPIO signals between user FPGA a...

Page 6: ...nector P6 on the card is not compatible with the VITA 42 10 XMC GPIO Standard In particular USB VCC must not be applied on this connector The ADM XRC 7V1 is compatible with either 5V or 12V on the VPW...

Page 7: ...ystem monitoring that measures the board and FPGA temperature It also includes a self protection mechanism that will clear the target FPGA configuration if an over temperature condition is detected Se...

Page 8: ...x x4 x4 x4 Not in X330T and X485T 39 34 117 118 115 119 116 114 113 12 HR 31 32 111 112 P6 x4 x8 SPI FLASH FLASH 64 GPIO 0 GPIO Level Converter Mux Unused FPGA Banks HR banks in X330T and 585T DDR3 Ba...

Page 9: ...e connected directly to the user FPGA Bridge FPGA is used PCIe lanes 3 0 are connected to the bridge SW1 4 Flash Boot Inhibit Target FPGA is not configured from onboard flash memory Target FPGA is con...

Page 10: ...figured Target FPGA is unconfigured D10 Green Bridge Done Bridge FPGA is configured Bridge FPGA is unconfigured D11 Amber Bridge Bypass Bridge FPGA is bypassed PCIe lanes 3 0 are connected directly to...

Page 11: ...Prohibit This signal is an input from the carrier When asserted high all writes to non volatile memories are inhibited This is indicated by the Amber LED D13 This signal cannot be internally driven o...

Page 12: ...4 JTAG Boundary Scan Chain If the boundary scan chain is connected to the interface at the XMC connector SW1 5 is ON Header J1 should not be used 3 3 2 XMC Interface The JTAG interface on the XMC conn...

Page 13: ...REFCLK0 REFCLK1 MGT117 REFCLK0 REFCLK1 MGT118 REFCLK0 REFCLK1 XMC P5 XMC P6 PCIe REFCLK Buffer PCIe Bridge 200MHZ Buffer 200MHZ Source XRM Interface User Programmable Source MGT119 REFCLK0 REFCLK1 No...

Page 14: ...K200M 200 MHz MGTREFCLK0_115 LVDS Y8 Y7 REFCLK200M 200 MHz MGTREFCLK0_118 LVDS G10 G9 Table 4 REFCLK200M Connections 3 4 2 PCIe Reference Clock 0 PCIEREFCLK0 The 100MHz PCI Express reference clock is...

Page 15: ...Global Clock GCLK_M2C The clock GCLK_M2C is a differential clock signal using LVDS It is provided by an XRM module through the XRM connector CN1 at pins 110 108 It is connected to an MRCC input on the...

Page 16: ...ual V1 9 23rd Aug 2016 Signal Frequency Target FPGA Input IO Standard P pin N pin XRM_PECL_CLK Variable IO_L13_T2_MRCC_15 LVDS AV40 AW40 Table 9 XRM_LVDS_CLK Connections Page 12 Functional Description...

Page 17: ...t WP pin is connected to an inverted version of the NVMRO signal at the XMC interface When the NVMRO signal is active High all writes to the flash will be inhibited This state will be indicated by the...

Page 18: ...finitions Note If an over temperature alert is detected from the System Monitor the target will be cleared by pulsing its PROG signal See Automatic Temperature Monitoring 3 6 2 Bridge Less Mode When o...

Page 19: ...idge Tranceiver Power AVCC 1 2V Target Tranceiver Power AVTT 1 2V Bridge Tranceiver Power AVTT 1 5V DDR3 SDRAM Target FPGA memory I O XRM_VIO Front Panel I O voltage 1 8V Target Tranceiver Power AVCC_...

Page 20: ...age due to over temperature It is possible that it will cause the user application and possibly the host computer to hang as a result of communication errors An overtemperature shutdown will not occur...

Page 21: ...NDARD required for each signal are given in the SDK IO Banks Voltage Purpose 0 14 1 8V Configuration JTAG LBus Control XMC Control Target SelectMap Interface 13 33 1 8V Pn4 Pn6 GPIO 15 16 17 XRM_VIO X...

Page 22: ...112 MGT113 MGT114 MGT115 MGT116 MGT117 MGT118 XMC P5 XMC P6 XRM Interface MGT119 PCIe Bridge RearMGT 3 0 RearMGT 7 4 RearMGT 8 11 RearMGT 12 15 RearMGT 16 17 RearMGT 16 17 XRM 3 0 XRM 7 4 Bridge Bypas...

Page 23: ...an ordering option The memory banks are arranged for compatibility with the Xilinx Memory Interface Generator MIG DRAM Banks Shows the component references and FPGA banks used Full details of the int...

Page 24: ...4 groups to the Target FPGA Each group consists of 16 standard I O pairs a Regional Clock Capable pair and either 2 or 4 single ended signals There are no on board terminations on the pairs and any c...

Page 25: ...OM that contains vital product information VPD such as part number serial number operating voltage and product specific information For designing custom XRMs contact Alpha Data for details on duplicat...

Page 26: ...ADM XRC 7V1 User Manual V1 9 23rd Aug 2016 Page Intentionally left blank Page 22 Functional Description ad ug 1248_v1_9 pdf...

Page 27: ...GND GND TMS GND GND 12V0 7 PET_P6 PET_N6 3V3 PET_P7 PET_N7 VPWR 8 GND GND TDI GND GND M12V0 9 VPWR 10 GND GND TDO GND GND GAO 11 PER_PO PER_NO MBIST_L PER_P1 PER_N1 VPWR 12 GND GND GA1 GND GND MPRESE...

Page 28: ...PN6_TX_N7 GP26 8 GND GND GP23 GND GND GP24 9 PN6_TX_P8 PN6_TX_N8 GP21 PN6_TX_P9 PN6_TX_N9 GP22 10 GND GND GP19 GND GND GP20 11 PN6_RX_P0 PN6_RX_N0 GP17 PN6_RX_P1 PN6_RX_N1 GP18 12 GND GND GP15 GND GN...

Page 29: ...5 13 GP11 AW33 13 GP12 AV33 13 GP13 AV34 13 GP14 AY33 13 GP15 AT35 13 GP16 AW30 13 GP17 AW32 13 GP18 AV31 13 GP19 AT31 13 GP20 AU32 13 GP21 AR30 13 GP22 AU31 13 GP23 AT32 13 GP24 AN20 33 GP25 AL24 33...

Page 30: ...ignal FPGA Pin FPGA Bank GP35 AN30 13 GP36 AL32 14 GP37 AL31 14 GP38 AN31 13 Table 19 Pn6 GPIO Pin Map GCC Global clock capable MRCC Multi region clock capable SRCC Single region clock capable Page 26...

Page 31: ...AU22 PN4_N14 PN4_P15 AY35 29 30 AU24 PN4_P16 PN4_N15 AW35 31 32 AV24 PN4_N16 PN4_P17 AT36 33 34 AR24 PN4_P18 PN4_N17 AU36 35 36 AT24 PN4_N18 PN4_P19 AT21 37 38 AV36 PN4_P20 PN4_N19 AU21 39 40 AW36 PN...

Page 32: ...5 E5 RearMGT_TX_6 M4 M3 P5 A7 P5 B7 RearMGT_TX_7 N2 N1 P5 D7 P5 E7 RearMGT_TX_8 P4 P3 P6 A1 P6 B1 RearMGT_TX_9 R2 R1 P6 D1 P6 E1 RearMGT_TX_10 T4 T3 P6 A3 P6 B3 RearMGT_TX_11 U2 U1 P6 D3 P6 E3 RearMGT...

Page 33: ...5 RearMGT_RX_13 AA6 AA5 P6 D15 P6 E15 RearMGT_RX_14 AB4 AB3 P6 A17 P6 B17 RearMGT_RX_15 AC6 AC5 P6 D17 P6 E17 RearMGT_RX_16 C6 C5 P6 A19 P6 B19 RearMGT_RX_17 D8 D7 P6 D19 P6 E19 Table 21 Target RearMG...

Page 34: ...two connectors CN1 and CN2 CN1 is a 180 way Samtec QSH in 3 fields It is for general purpose signals power and module control CN2 is a 28 way Samtec QSE DP for high speed serial MGT links Power JTAG P...

Page 35: ...2 19 20 AA42 DA_N9 DA_N10 AA32 21 22 AD30 DA_N11 DA_P10 AA31 23 24 AC30 DA_P11 DA_N12 AB42 25 26 Y39 DA_P13 DA_P12 AB41 27 28 AA39 DA_N13 DA_N14 AA30 29 30 AB29 DA_P15 DA_P14 AA29 31 32 AC29 DA_N15 DB...

Page 36: ...4 AF37 85 86 BB41 DB_N15 DB_P14 AE37 87 88 BA41 DB_P15 DB_CC_P16 AV40 89 90 AB34 SB_1 DB_CC_N16 AW40 91 92 AU37 SC_0 SA_1 Y38 93 94 AM38 SC_1 SB_0 Y34 95 96 AL39 SD_0 DC_CC_P16 AU38 97 98 AM42 DC_N1 D...

Page 37: ...143 144 AW38 DC_P13 DC_N14 AR40 145 146 AD42 DD_P1 DC_P14 AP40 147 148 AE42 DD_N1 DD_P0 AB38 149 150 BB37 DC_N15 DD_N0 AB39 151 152 BA37 DC_P15 DD_P2 AJ40 153 154 AG41 DD_N3 DD_N2 AJ41 155 156 AF41 D...

Page 38: ...N1 MGT_C2M_P4 AK4 9 10 AG6 MGT_M2C_P4 MGT_C2M_N4 AK3 11 12 AG5 MGT_M2C_N4 MGT_C2M_P5 AJ2 13 14 AF4 MGT_M2C_P5 MGT_C2M_N5 AJ1 15 16 AF3 MGT_M2C_N5 MGT_C2M_P2 AM4 17 18 AL6 MGT_M2C_P2 MGT_C2M_N2 AM3 19...

Page 39: ...rease uC threshold and added Maximum Memory Speeds 6 Feb 2015 1 5 K Roth Updated JTAG Interface to use appropriate JTAG reference designator 6 Feb 2015 1 6 K Roth Updated JTAG Interface to use appropr...

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