Alpha Data ADM-XRC-7V1, User Manual

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ADM-XRC-7V1 User Manual
V1.9 - 23rd Aug 2016
3.4.4 Programmable Clocks (LCLK, PROGCLK 0-3)
There are two programable clock sources that are forwarded throughout the FPGA. These clocks are
programmable through the Alpha Data ADM-XRC Gen 3 SDK. LCLK is generated in the Bridge FPGA by the the
Alpha Data ADB3 driver and offers a less accurate frequency resolution, but with a wider programmable
frequency range. PROGCLK[3:0] is generated by a dedicated programmable clock generator IC and offer
extremely high frequency resolutions (1ppm increments). PROGCLK[3:0] is generated by a single source and
buffered to all MGT tiles.
Signal Frequency Target FPGA Input IO Standard "P" pin "N" pin
LCLK 5 - 700 MHz IO_L13_MRCC_14 LVDS AJ32 AK32
PROGCLK0 5 - 312.5 MHz MGTREFCLK1_113 LVDS AK8 AK7
PROGCLK1 5 - 312.5 MHz MGTREFCLK1_115 LVDS AB8 AB7
PROGCLK2 5 - 312.5 MHz MGTREFCLK1_117 LVDS M8 M7
PROGCLK3 5 - 312.5 MHz MGTREFCLK1_119 LVDS C10 C9
Table 6 : PROGCLK Connections
3.4.5 Module-Carrier Global Clock (GCLK_M2C)
The clock "GCLK_M2C" is a differential clock signal using LVDS. It is provided by an XRM module through the
XRM connector, CN1, at pins 110 & 108. It is connected to an MRCC input on the Target FPGA.
Signal Frequency Target FPGA Input IO Standard "P" pin "N" pin
GCLK_M2C Variable IO_L13_T2_MRCC_17 LVDS AF39 AF40
Table 7 : GCLK_M2C Connections
3.4.6 Module-Carrier MGT Clock (MGTCLK_M2C)
The reference clock "MGTCLK_M2C" is a differential clock signal using LVDS. The clock is provided by an XRM
module through the XRM connector, CN1, at pins 109 & 111. It is first buffered and fanned out, then connected
to GTX Quads 113 and 114 on the Target FPGA for application specific frequencies / line rates.
Signal Frequency Target FPGA Input IO Standard "P" pin "N" pin
MGTCLK_M2C Variable MGTREFCLK0_113 LVDS AH8 AH7
MGTCLK_M2C Variable MGTREFCLK0_114 LVDS AD8 AD7
Table 8 : MGTCLK_M2C Connections
3.4.7 XRM LVDS Clock (XRM_LVDS_CLK)
The clock "XRM_LVDS_CLK" is a differential clock signal using LVDS levels. The clock is provided by the target
FPGA and connected to an XRM module through the XRM connector, CN1, at pins 113 & 115.
Page 11 Functional Description
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