ADM-XRC-7V1 User Manual
V1.9 - 23rd Aug 2016
3.2 XMC Platform Interface
3.2.1 IPMI I2C
A 4 Kbit I2C EEPROM (type M24C04) is connected to the XMC IPMI. This memory contains board information
(type, voltage requirements etc.) as defined in the XMC based specification.
3.2.2 MBIST#
Built-In Self Test. This output signal is driven active (low) until the FPGA with PCIe interface is configured. In
normal operation, this is the bridge FPGA. In Bridge Bypass mode or Bridge-Less Mode, it is the target FPGA.
3.2.3 MVMRO
XMC Write Prohibit. This signal is an input from the carrier. When asserted (high), all writes to non-volatile
memories are inhibited. This is indicated by the Amber LED, D13.
This signal cannot be internally driven or over-ridden. A buffered version of the signal is connected to the target
FPGA at pin AG32.
3.2.4 MRSTI#
XMC Reset In. This signal is an active low input from the carrier. When asserted, the bridge FPGA will be reset.
The MRSTI# signal is translated to 1.8V levels and connected to the target FPGA at pin AF30.
3.2.5 MRSTO#
XMC Reset Out. This optional output signal is unused and undriven.
3.2.6 MPRESENT#
Module Present. This output signal is connected directly to 0V.
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Functional Description
ad-ug-1248_v1_9.pdf
