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Verification Manual
1
Performance Tests
External Clock Reference Inputs and Clock Reference Output
Specifications
Description
The test uses a PDH/DSn test set and a Frequency Counter
connected to the appropriate external Clock input and output
ports. When the Transmitter is set to external Clock the
reference Clock output port timing and signal rate generation is
derived from the external Clock source.
Clock Rate
Description
2.048 Mb/s MTS
Accepts timing reference as per ITU-T
G.703-1998
2.048 MHz Clock
Accepts timing reference as per ITU-T
G.703-1998
1.544 Mb/s BITS
Accepts DS-1 timing reference as per
TA-TSY-000378
N O T E
The 2 MHz input is only available when SDH or En rate is selected on the
Transmitter. The DS1 input is only available when SONET or T-Carrier rate
is selected on the Transmitter.
BITS Clock is not a binary format signal. Signal is a Ternary All 1’s DS-1
signal with ESF Framing, clocked at 1.544 MHz.
Verification.book Page 24 Monday, January 19, 2004 1:40 PM
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