AEROFLEX GAISLER
66
RT-SPW-ROUTER
Copyright Aeroflex Gaisler AB
June 2012, Version 1.2
PCI address are set by mapping registers, while the least significant bits are directly transferred from
the AMBA backend. A separate mapping register is implemented for each AMBA master.
To generate PCI memory accesses, the following steps must be executed. The master function must be
enabled, preferably by the PCI system host during the PCI configuration and the mapping register
must be programmed with the most significant bits of the PCI address that should be accessed. After
this, read and write accesses to the AMBA backend will be transferred the corresponding PCI address.
PCI I/O cycles: Accesses to the lower half of the AHB I/O bank is translated to PCI I/O cycles. The
upper 16 bits of the PCI address are defined by a mapping register (AMBA to PCI mapping for PCI I/
O cycles) while the lower 16 bits are transferred form the AMBA bus.
To generate PCI I/O accesses, The master function must be enabled, preferably by the PCI system
host during the PCI configuration and the mapping register must be programmed with the most signif-
icant bits of the PCI address that should be accessed. After this, read and write accesses to the lower
half of the AHB I/O bank will be translated to “I/O read” and “I/O write” on the PCI bus.
PCI configuration cycles: Accesses to the upper half of the AHB I/O bank translates to PCI configu-
ration cycles. The upper 21 bits of the PCI address is calculated from bit 15:11 of the AMBA address
(PCI_address[AMBA_address[15:11] + 10] = ‘1’). When AMBA_address[15:11] is equal to zero, the
core makes accesses to its own PCI configuration space (this will not generate any accesses on the
PCI bus). The lower 11 bits of the PCI address is transferred from AMBA address except for bit 1 and
0 which are always set to zero. Accesses to the core’s own PCI configuration space are allowed before
the master function is enabled, to be able to enable the master. Note: When in peripheral slot, configu-
ration cycles must not be initiated.
5.2.2
PCI Target
The PCI target function can be enabled and disabled in the PCI configuration space. When enabled,
the PCI target accepts “Memory read”, “Memory read multiple”, and “Memory write” commands for
data accesses. Access to the PCI configuration space is provided for “Configuration read” and “Con-
figuration write” commands. When the PCI target is accessed (except for Configuration read/write),
the core transfers this access to the AMBA backend. The most significant bits of the address used by
the AMBA backend is controlled by a mapping register, while the least significant bits of the address
are directly transferred from the PCI access. A separate mapping register is implemented for PCI
BAR 1 - 4.
The following configuration steps are required for the PCI target to correctly respond to data accesses.
The target must be setup to accept memory accesses, preferably by the PCI system host during PCI
configuration. The mapping register must be programmed with the most significant bits of the AMBA
address. After this configuration, accesses to the PCI target interface are transferred to the AMBA
bus.
The PCI target interface provides three PCI memory bars: BAR 0 enables access to the configuration
registers; BAR 1 is used for data transfers; BAR 5 is used by the master function and should never be
accessed by any other master on the PCI bus.
5.2.3
Configuration
The core has configuration registers accessible via the AMBA APB interface and via the PCI BAR 0.
The PCI BAR to AMBA address mapping registers and the interrupt controller registers are accessible
via the PCI BAR 0. The interrupt registers must be setup to enable interrupt handling. The PCI to
AMBA address mapping registers must be setup to translate the PCI access into the correct AMBA
access. These mapping registers are also accessible via the AMBA APB interface. The AMBA to PCI
