AEROFLEX GAISLER
63
RT-SPW-ROUTER
Copyright Aeroflex Gaisler AB
June 2012, Version 1.2
4.3
Receiver interface
The receiver interface consists of the following signals connected to the receiver FIFO: rxicharav, rxi-
charcnt, rxichar, rxiread. Rxicharav is asserted when there are one or more characters available in the
receiver FIFO while rxicharcnt shows the actual number available. Rxiread should be asserted for one
cycle when rxicharav is asserted to read out a character. The character will be available on rxichar the
cycle following the assertion of rxiread. Figure 16 shows an example of reading characters from the
receiver FIFO.
4.3.1
Link errors
When an link error occurs during reception an EEP is automatically inserted into the Receiver FIFO if
the previous character written to the FIFO was not an EOP or EEP.
4.4
Transmitter interface
The transmitter interface consists of the following signals: txiwrite, txichar, txiflush, txicharcnt, txi-
full. Txifull is asserted when the transmitter FIFO is full while txicharcnt shows the actual number of
characters currently in the FIFO. Txiwrite should be asserted for one cycle to write the value on txi-
char into the FIFO. Txiflush should be asserted for one cycle to discard all characters in the FIFO. No
Figure 15. Receiving time-codes using tickout, timeout and timectrlout.
timeout
tickout
clk
timectrlout
T0
T1
C0
C1
Figure 16. Receiving characters through the FIFO interface.
rxichar
rxiread
clk
D0
D1
rxicharav
1
1
rxicharcnt
0
0
0
