AEROFLEX GAISLER
10
RT-SPW-ROUTER
Copyright Aeroflex Gaisler AB
June 2012, Version 1.2
2.6
Signals
The common architecture has the external signals shown in table 10.
Table 10. External signals
Name
Usage
Direction
Polarity
CID
clk
Main system clock
In
-
All
resetn
System reset
In
Low
All
dsutx
Debug UART transmit data
Out
Low
2
dsurx
Debug UART receive data
In
Low
2
dsutck
Debug JTAG Clock
In
-
-
dsutms
Debug JTAG Mode
In
High
-
dsutdi
Debug JTAG Input
In
High
-
dsutdo
Debug JTAG Output
Out
High
-
rxclk
SpaceWire link receive clock
In
-
All
txclk
SpaceWire link transmit clock
In
-
All
spw_rxdp[7:0]
Data input, positive
In, LVDS
High
All
1) 3)
spw_rxdn[7:0]
Data input, negative
In, LVDS
Low
All
1) 3)
spw_rxsp[7:0]
Strobe input, positive
In, LVDS
High
All
1) 3)
spw_rxsn[7:0]
Strobe input, negative
In, LVDS
Low
All
1) 3)
spw_txdp[7:0]
Data output, positive
Out, LVDS
High
All
1) 3)
spw_txdn[7:0]
Data output, negative
Out, LVDS
Low
All
1) 3)
spw_txsp[7:0]
Strobe output, positive
Out, LVDS
High
All
1) 3)
spw_txsn[7:0]
Strobe output, negative
Out, LVDS
Low
All
1) 3)
spw_rxd[7:0]
Data input
In,
High
All
2) 3)
spw_rxs[7:0]
Strobe input
In
High
All
2) 3)
spw_txd[7:0]
Data output
Out
High
All
2) 3)
spw_txs[7:0]
Strobe output
Out
High
All
2) 3)
timecodeen
Enable time-code functionality
In
High
1
tickin[1:0]
Tick input signals for FIFO interfaces
In
High
1
timein0[7:0]
Time input signals for FIFO 0 interface
In
-
1
timein1[7:0]
Time input signals for FIFO 1 interface
In
-
1
tickout[1:0]
Tick output signals for FIFO interfaces
Out
High
1
timeout0[7:0]
Time output signals for FIFO 0 interface
Out
-
1
timeout1[7:0]
Time output signals for FIFO 1 interface
Out
-
1
rxread[1:0]
Receiver FIFO read signals for FIFO interfaces
In
High
1
rxchar0[8:0]
Receiver character signals for FIFO 0 interface
Out
-
1
rxchar1[8:0]
Receiver character signals for FIFO 1 interface
Out
-
1
txwrite[1:0]
Transmitter FIFO write signals for FIFO interfaces
In
High
1
txchar0[8:0]
Transmitter character signals for FIFO 0 interface
In
-
1
txchar1[8:0]
Transmitter character signals for FIFO 1 interface
In
-
1
txfull[1:0]
Transmitter full signal for FIFO interfaces
Out
High
1
