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Aeroflex Gaisler RT-SPW-ROUTER, User Manual

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Aeroflex Gaisler RT-SPW-ROUTER User Manual Download Page 5

AEROFLEX GAISLER

5

RT-SPW-ROUTER

Copyright Aeroflex Gaisler AB

June 2012, Version 1.2

1

Introduction

1.1

Overview

The SpaceWire Router family is based on a common architecture from which standard configurations
are derived. The architecture is centered around the a non-blocking switch matrix which can connect
any input port to any output port.

All the addressing modes such as path, logical and regional logical are supported. Group adaptive
routing is fully supported, meaning that both path and logical addresses can be individually config-
ured to use from one up to all ports. A unique feature is the support for packet distribution, which can
be used to implement multicast and broadcast addresses. Output ports are arbitrated using two priority
levels with a round-robin scheme within each level.

The 10x SpaceWire router implements 8 external SpaceWire ports and 2 external FIFO ports. The
SpaceWire and FIFO interfaces are directly connected to the switch matrix.

The 6x SpaceWire router implements 4 external SpaceWire ports and a PCI initiator and target inter-
face (32-bit, 33 MHz) accessed via two internal AMBA ports with DMA and RMAP. In this configu-
ration, the AMBA Advanced High-speed Bus (AHB), to which the AMBA ports and the PCI interface
are connected, is used for high-speed communication between the switch matrix and the external PCI
interface. Supporting low-bandwidth items, such as configuration registers, are connected to the
AMBA Advanced Peripheral Bus (APB) which is accessed through an AHB to APB bridge.

The full SpaceWire router architecture includes the following modules: SpaceWire Router, PCI Initia-
tor/Target Interface, AMBA AHB Debug UART and AMBA AHB Status Register.

1.2

Standard configurations

Due to resource limitations, it is not possible to fit the full SpaceWire router architecture on a single
device. Therefore, sub-set configurations have been defined to suit applications with different inter-
facing needs. Table 1 below shows which functions are available in each of the configurations.

Table 1. Standard configurations

Configuration name

10x SpaceWire Router

6x SpaceWire Router with PCI

Configuration ID (CID)

1

2

SpaceWire Ports

8

4

FIFO Ports

2

AMBA Ports with RMAP

2

Configuration port with RMAP

Yes

Yes

Configuration port with AMBA

Yes

PCI Initiator/Target and Interrupt Controller

Yes

AMBA Status Register

Yes

UART Debug Link

Yes

JTAG Debug Link

FPGA and Package

Actel RTAX2000S CCGA624

Actel RTAX2000S CCGA624

Actel RTAX2000S CQFP352

Actel RTAX2000S CQFP352

Actel RT3PE3000L CCGA484

SpaceWire Physical Layer

LVTTL / LVDS (on-chip)

LVTTL / LVDS (on-chip)

Summary of Contents for RT-SPW-ROUTER

Page 1: ...available as standard components using the Actel RTAX and RT ProASIC3 FPGAs The fault tolerant design of the router in combination with the radiation tolerant FPGA makes it ideally suited for space an...

Page 2: ...ort disable 14 3 2 7 Timers 14 3 2 8 On chip memories 16 3 2 9 System time distribution 17 3 2 10 Invalid address error 17 3 2 11 Global configuration features 17 3 3 SpaceWire ports 18 3 4 FIFO ports...

Page 3: ...65 5 2 1 PCI Initiator 65 5 2 2 PCI Target 66 5 2 3 Configuration 66 5 2 4 Byte access 67 5 2 5 Error response 67 5 2 6 Interrupt controller generation of PCI interrupt 67 5 3 Registers 68 5 4 Signal...

Page 4: ...AHB APB bridge with plug play support 84 12 1 Overview 84 12 2 Operation 84 12 2 1 Decoding 84 12 2 2 Plug play information 84 13 Electrical description 85 13 1 Absolute maximum ratings 85 13 2 Operat...

Page 5: ...Bus AHB to which the AMBA ports and the PCI interface are connected is used for high speed communication between the switch matrix and the external PCI interface Supporting low bandwidth items such a...

Page 6: ...G Debug Link PCI pci_clk pci_gnt pci_rst pci_idsel pci_stop pci_perr pci_frame pci_devsel pci_int pci_irdy pci_par pci_trdy pci_ad 31 0 pci_cbe 31 0 pci_req pci_serr Initiator Target txclk Time Code I...

Page 7: ...nterrupts are raised All interrupts are han dled by the interrupt controller and forwarded to the PCI bus Note that this only applies to CID 2 Table 2 Used IP cores Core Function Vendor Device CID AHB...

Page 8: ...e shown in table 6 and is based on the AMBA AHB address space Note that this only applies to CID 2 Table 4 AMBA AHB address range Core Address range Area CID PCIF 0x00000000 0x3FFFFFFF PCI memory area...

Page 9: ...play information for APB slaves Core Index Function Address range CID GRSPWROUTER 0 AMBA port 0 0xFFEFF000 0xFFEFF017 2 GRSPWROUTER 1 AMBA port 1 0xFFEFF018 0xFFEFF01F 2 PCIF 2 PCI Initiator Target 0x...

Page 10: ...itive Out LVDS High All 1 3 spw_txsn 7 0 Strobe output negative Out LVDS Low All 1 3 spw_rxd 7 0 Data input In High All 2 3 spw_rxs 7 0 Strobe input In High All 2 3 spw_txd 7 0 Data output Out High Al...

Page 11: ...the port control registers In High All selfaddren Reset value for selfaddren register bit In High All linkstartreq Reset value for the linkstartreq register bit In High All autodconnect Reset value fo...

Page 12: ...aths with read write signals Lastly the AMBA ports transfer characters from and to an AHB bus using DMA The four different port types are described in further detail in sections 3 3 3 4 3 5 and 3 6 3...

Page 13: ...to the output corresponding to the path address in the packet even if the port setup register has not been initialized For group adaptive routing and packet distribution to be used the port setup reg...

Page 14: ...ed for packet distribu tion is busy the router will wait for it to become free before transmitting on any of the ports Due to the wormhole routing implementation the slowest link will determine the sp...

Page 15: ...dis tribution 3 2 7 2 Timer enabled and output port not in run state The timer is started when the packet arrives and if the link has not entered run state until the timer expires the packet will be...

Page 16: ...rx tx which are 9 wide The FIFO ports have the exact same FIFO configuration as the SpaceWire ports The AMBA ports have one 9 bit wide receiver FIFO and two 32 bit wide AHB FIFOs Parity is used to pro...

Page 17: ...so time codes will be accepted regardless of their value If the TF bit in the router configuration status register is set to 1 time code control flag filtering is enabled and the time codes are requi...

Page 18: ...tarted until a 0 is written to the linkstart bit of the port or if the auto discon nect feature is enabled see next section 3 2 11 3 Auto disconnect If the link was started by the link start feature t...

Page 19: ...Figure 3 illustrates the read operation Note that rxcharav would only be deasserted as illustrated in the figure if the FIFO contained 4 characters Each time rxread is asserted on the rising edge of t...

Page 20: ...of the maximum link bitrate 3 4 5 Bridge mode The FIFO ports normally operate in standard mode which has been described so far in this section But they can also be set in bridge mode through the brid...

Page 21: ...hannels using an AHB master interface 3 5 2 Operation The main sub blocks of the router AHB interfaces are the DMA engines the RMAP target and the AMBA interface A block diagram of the internal struct...

Page 22: ...one in the configuration port When the RMAP target is not present or disabled there is no need to include a protocol ID in the packets and the data can start immediately after the address All packets...

Page 23: ...l it is cleared by writing a one to it The current time counter value can be read from the time register It is updated each time a Time code is received and the timerxen bit is set The same register i...

Page 24: ...the invalid address error code The packet is only discarded up to and including the next EOP EEP if an address match cannot be found and the RMAP target is dis abled Packets other than RMAP commands...

Page 25: ...mmand No Yes No Set DMA channel number to 0 Process RMAP command Separate addressing No Yes dma n addr rxaddr dma n mask Channel enabled Increment channel number and pid 1 and defaddr defmask rxaddr d...

Page 26: ...sing and the RMAP target while the separate address provides the channel its own range If all channels use the default registers they will accept the same address range and the enabled channel with th...

Page 27: ...receiver is enabled and the address falls into the accepted address range the next state is entered where the rxdescav bit is checked This bit indicates whether there are active descriptors or not an...

Page 28: ...d the length of the header is determined by checking byte 3 which should be the command field The calculated CRC value is then checked when the header has been received according to the calculated num...

Page 29: ...enabled the port reads them and transfer the amount data indicated 3 5 4 2 Setting up the core for transmission Four steps need to be performed before transmissions can be done with the port First th...

Page 30: ...from this pointer A null CRC will be sent if the length of the data field is zero 16 Append header CRC HC Append CRC calculated according to the RMAP specification after the data sent from the header...

Page 31: ...ssion is active No transmission is active if the transmit enable bit is zero and the complete table has been sent or if the table is aborted explained below If the table is aborted one has to wait unt...

Page 32: ...protocol RMAP is a protocol which is designed to provide remote access via a SpaceWire network to memory mapped resources on a SpaceWire node It has been assigned protocol ID 0x01 It provides three op...

Page 33: ...rite commands are divided into two subcategories when examining their capabilities verified writes and non verified writes Verified writes have a length restriction of 4 bytes and the address must be...

Page 34: ...to the DMA channel There is a possibility that RMAP commands will not be performed in the order they arrive This can happen if a read arrives before one or more writes Since the target stores replies...

Page 35: ...ply is sent 0 1 0 1 0 1 Not used Does nothing No reply is sent 0 1 0 1 1 0 Not used Does nothing Reply is sent with error code 2 0 1 0 1 1 1 Read Mod ify Write increment ing address Executed normally...

Page 36: ...ing is done Same alignment restric tions apply as for rmw If they are violated nothing is done No reply is sent 0 1 1 1 1 0 Write single address ver ify before writing send acknowledge Executed normal...

Page 37: ...smaller Shorter accesses are also done during descriptor reads and status writes The AHB master also supports non incrementing accesses where the address will be constant for sev eral consecutive acce...

Page 38: ...ress 0xC Reserved 0x10 Destination key 0x14 Time 0x20 DMA channel 1 control status 0x24 DMA channel 1 rx maximum length 0x28 DMA channel 1 transmit descriptor table address 0x2C DMA channel 1 receive...

Page 39: ...D r 8 Tick out IRQ TQ Generate interrupt when a valid time code is received rw 7 RESERVED t 6 Reset RS Make complete reset of the SpaceWire node Self clearing rw 5 Promiscuous Mode PM Enable Promiscuo...

Page 40: ...SpaceWire network Reset value 254 rw Table 24 AMBA port destination key 31 8 7 0 RESERVED DESTKEY NA 0x00 31 8 RESERVED r 7 0 Destination key DESTKEY RMAP destination key rw Table 25 AMBA port time r...

Page 41: ...s detected on the AHB bus while this receive DMA channel was accessing the bus wc 7 TX AHB error TA An error response was detected on the AHB bus while this transmit DMA channel was accessing the bus...

Page 42: ...ptor table base address DESCBASEADDR Sets the base address of the descriptor table Not reset rw 9 3 Descriptor selector DESCSEL Offset into the descriptor table Shows which descriptor is cur rently us...

Page 43: ...one or more of the configuration access disable options being enabled a reply with sta tus set to authorization failure will be sent if requested If a reply is not requested the packet will be silentl...

Page 44: ...e the same restrictions as the verified writes As in the verified write case the increment ing bit can be set to any value since only one operation will be performed for each command Too much data is...

Page 45: ...violated error code is set to 10 0 1 0 0 1 1 Read incre menting address Supported Address has to be word aligned and belonging to the defined address range data length has to be 4 Reply is sent If ali...

Page 46: ...ent 0 1 1 0 1 1 Write incre menting address do not verify before writ ing send acknowledge Not implemented Command is not executed Error code is set to 10 and a Reply is sent 0 1 1 1 0 0 Write single...

Page 47: ...these errors are detected the error code is set to 10 Reply is sent 0 1 1 1 1 1 Write incre menting address ver ify before writing send acknowledge Supported Length must be 4 address must be word alig...

Page 48: ...finitions Table 33 Reset value definitions Value Description 0 Reset to value 0 1 Reset to value 1 0x0 Hexadecimal value which can be used for multibit fields NA Not applicable For example reserved fi...

Page 49: ...individual bit enables when set to 1 packets with the path or logical address corresponding to this port setup register to be sent on the port with the same num ber as the bit index Only bits up to an...

Page 50: ...the packet is discarded Note that the corresponding port setup register must not be set to 0 when a routing table entry is enabled rw 1 Priority PR Sets the arbitration priority of this port 0 low pri...

Page 51: ...ted to but the other destination ports will still be transmitted to Port 1 cannot be disabled and this bit is read only 0 in that case rw 9 Timer enable TR Enable timer for packet transfer timeouts fo...

Page 52: ...emory error ME Uncorrectable parity error detected in FIFO memories on this link wc 16 Transmit FIFO full TF Set to 1 when the transmit FIFO on this port is full r 15 Receive FIFO empty RE Set to 1 wh...

Page 53: ...ycles Thus when writing this register through RMAP the reply bit should NOT bet set since the reply will not be sent rw 6 Auto disconnect AD When set to 1 ports will be automatically stopped after a t...

Page 54: ...16 15 8 7 0 MAJOR VERSION MINOR VERSION PATCH INSTANCE ID NA NA NA 31 24 Major version MAJOR VERSION Holds the major version number of the router r 23 16 Minor version MINOR VERSION Holds the minor v...

Page 55: ...When set to 0 writes are not allowed except to this register Write or RMW commands will be replied with an authorization error if a reply was requested rw Table 48 Timer prescaler 31 16 16 1 0 RESERV...

Page 56: ...3 High spw_txd Output LVTTL Data output positive 2 3 High Logical 0 spw_txs Output LVTTL Strobe output positive 2 3 High Logical 0 timecodeen Input Enable time code functionality High tickin Input Ti...

Page 57: ...r the timer prescaler Mapped to bits of the prescaler register 4 reload_timer Input Reset value for the port timer registers Mapped to bits of the timer registers 4 timeren Input Reset value for the t...

Page 58: ...tSPW2 input to clock hold not applicable tSPW3 input to clock setup not applicable tSPW4 output data bit period clk periods 5 500 ns tSPW5 input data bit period 5 500 ns tSPW6 data strobe edge separat...

Page 59: ...delay rising clk edge 4 14 ns tSPWFIFO4 clock to output delay rising clk edge 4 14 ns tSPWFIFO5 txchar timein input to clock setup rising clk edge 19 ns tSPWFIFO6 txchar timein input from clock hold...

Page 60: ...ransmitter and the link interface FSM They handle communication on the SpaceWire net work The PHY blocks provides a common interface for the receiver to the four different data recov ery schemes and i...

Page 61: ...e allowed The credit counter incoming credits is automatically increased when FCTs are received and decreased when N Chars are transmitted Received N Chars are stored to the receiver N Char FIFO while...

Page 62: ...ignal It is transmitted each time tickin is kept asserted until the tickin_done output is asserted Time codes are only transmitted when the link interface FSM is in run state and when the previous cha...

Page 63: ...nk errors When an link error occurs during reception an EEP is automatically inserted into the Receiver FIFO if the previous character written to the FIFO was not an EOP or EEP 4 4 Transmitter interfa...

Page 64: ...IFO 4 4 1 Link errors When a link error occurs characters read from the transmitter FIFO by the transmission logic will be discarded up to and including the next EOP or EEP character 4 5 Registers The...

Page 65: ...tion is performed inside the core through FIFOs The AMBA interface is extended with the GRLIB plug play information 5 2 Operation 5 2 1 PCI Initiator The PCI initiator can be enabled and disabled in t...

Page 66: ...core s own PCI configuration space are allowed before the master function is enabled to be able to enable the master Note When in peripheral slot configu ration cycles must not be initiated 5 2 2 PCI...

Page 67: ...matically resets the error bits in the PCI configuration space and saves the error status in its status register 5 2 6 Interrupt controller generation of PCI interrupt The interrupt controller monitor...

Page 68: ...for PCI BAR 2 0x08 PCI to AMBA mapping for PCI BAR 3 0x0C PCI to AMBA mapping for PCI BAR 4 0x10 Reserved 0x14 AMBA to PCI address mapping for PCI I O cycles 0x18 Status register 0x1C Input interrupt...

Page 69: ...able 57 PCIF Input interrupt mask 31 0 RESERVED 31 0 RESERVED Table 58 PCIF AMBA master to PCI address mapping register 31 30 29 0 PCI address RESERVED 31 30 MBS of the PCI address 29 0 RESERVED Table...

Page 70: ...D 3 0 Interrupt status Table 62 PCIF Interrupt clear register 31 16 15 1 0 RESERVED IC 15 1 31 16 RESERVED 15 1 Interrupt clear n IC n Writing 1 to IC n will clear interrupt n 0 RESERVED Table 63 PCIF...

Page 71: ...ci_ad 31 0 Input Output Address and Data bus High Tri state pci_cbe 3 0 Input Output Bus command and byte enable Low Tri state pci_par Input Output Parity signal High Tri state pci_frame Input Output...

Page 72: ...g Dose Test Report can be used to degrade the timing more accurately typical degradation is within 1 after 300 krad Si The functional behavior of the part is guaranteed up to 300 krad Si Table 65 Timi...

Page 73: ...fault tolerant units containing EDAC have a correctable error signal which is asserted each time a single error is detected When such an error is detected the effect will be the same as for an AHB err...

Page 74: ...nd zero otherwise 8 NE New Error Deasserted at start up and after reset Asserted when an error is detected Reset by writing a zero to it 7 The HWRITE signal of the AHB transaction that caused the erro...

Page 75: ...control byte followed by a 32 bit address followed by optional write data Write access does not return any response while a read access only returns the read data Data is sent on 8 bit basis as shown...

Page 76: ...value is latched into the reload register and the BL bit is set in the UART control register If the BL bit is reset by software the baud rate discovery process is restarted The baud rate discovery is...

Page 77: ...scribed in table 70 7 5 Timing The timing waveforms and timing parameters are shown in figure 28 and are defined in table 71 Note The dsurx input is re synchronized internally The signal does not have...

Page 78: ...read access is performed and data is ready to be shifted out of the data register Write access is performed by shifting in command AHB size and AHB address into the command data register fol lowed by...

Page 79: ...address 31 30 AHB Data AHB write read data For byte and half word transfers data is aligned according to big endian order where data with address offset 0 data is placed in MSB bits Table 74 Signal de...

Page 80: ...for the RTAX2000S SL parts is accord ing to Actel Total Ionizing Dose Test Report 10 at 300 krad Si The above specified timing values are guaranteed up to 50 krad Si If a higher total ionizing dose i...

Page 81: ...nals and their reset values are described in table 78 10 3 Timing The timing waveforms and timing parameters are shown in figure 32 and are defined in table 79 Note The resetn input is re synchronized...

Page 82: ...slave can occupy any binary aligned address space with a size of 1 4096 Mbyte A specific I O area is also decoded where slaves can occupy 256 byte 1 Mbyte The default address of the I O area is 0xFFF0...

Page 83: ...VERSION IRQ 31 24 23 12 11 5 4 0 31 20 19 16 15 4 3 0 Identification Register 00 10 9 HADDR P MASK TYPE C 0 0 ADDR P MASK TYPE C 0 0 ADDR P MASK TYPE C 0 0 ADDR P MASK TYPE C 0 0 ADDR P MASK TYPE C 0...

Page 84: ...igned address space with a size of 256 bytes 1 Mbyte 12 2 2 Plug play information The plug play information is mapped on a read only address area at the top 4 kbytes of the bridge address space Each p...

Page 85: ...ltages leakage currents and capacitances According to Actel data sheet RTAX and RT3PE 13 4 Output voltages leakage currents and capacitances According to Actel data sheet RTAX and RT3PE All output tim...

Page 86: ...dsutck in U23 LVCMOS 2 5 None Debug JTAG clock dsutms in V23 LVCMOS 2 5 None High Debug JTAG mode dsutdi in Y24 LVCMOS 2 5 None High Debug JTAG input dsutdo out V22 LVCMOS 2 5 Low 12 35 None High Deb...

Page 87: ...VDS 2 5 High SpaceWire strobe All 1 spw_txsn 3 out V22 LVDS 2 5 Low All 1 spw_rxdp 4 in LVDS 2 5 High SpaceWire data 1 1 spw_rxdn 4 in LVDS 2 5 Low 1 1 spw_rxsp 4 in LVDS 2 5 High SpaceWire strobe 1 1...

Page 88: ...3 3 High 8 35 None High SpaceWire strobe All 2 spw_rxd 2 in K24 LVTTL 3 3 None High SpaceWire data All 2 spw_rxs 2 in M21 LVTTL 3 3 None High SpaceWire strobe All 2 spw_txd 2 out N17 LVTTL 3 3 High 8...

Page 89: ...3 LVTTL 3 3 High 8 35 None Time output for FIFO 0 LSB 1 timeout0 1 out N9 LVTTL 3 3 High 8 35 None 1 timeout0 2 out J3 LVTTL 3 3 High 8 35 None 1 timeout0 3 out J4 LVTTL 3 3 High 8 35 None 1 timeout0...

Page 90: ...0 1 in J20 LVTTL 3 3 None 1 txchar0 2 in J23 LVTTL 3 3 None 1 txchar0 3 in L19 LVTTL 3 3 None 1 txchar0 4 in F24 LVTTL 3 3 None 1 txchar0 5 in G24 LVTTL 3 3 None 1 txchar0 6 in K18 LVTTL 3 3 None 1 tx...

Page 91: ...s 1 in A7 LVTTL 3 3 Up All reload_ps 2 in A6 LVTTL 3 3 Up All reload_ps 3 in G9 LVTTL 3 3 Up All reload_ps 4 in M4 LVTTL 3 3 Up All reload_ps 5 in P1 LVTTL 3 3 Up All reload_timer 0 in G8 LVTTL 3 3 Up...

Page 92: ...byte enable LSB 2 pci_cbe 1 inout W9 PCI 3 3 2 pci_cbe 2 inout AE4 PCI 3 3 2 pci_cbe 3 inout AE5 PCI 3 3 PCI byte enable MSB 2 pci_ad 0 inout W11 PCI 3 3 PCI address data LSB 2 pci_ad 1 inout W12 PCI...

Page 93: ...d RT3PE Note 1 These signals are only used in configuration with on chip LVDS drivers Note 2 These signals are only used in configuration with off chip LVDS drivers pci_ad 16 inout AC8 PCI 3 3 2 pci_a...

Page 94: ...I O All VCCIB6 50 62 68 80 3 3 V supply voltage for I O All VCCIB7 8 20 26 38 2 5 V supply voltage for I O TBD All VCCIB7 8 20 26 38 2 5 V supply voltage for I O TBD All VPUMP 267 Voltage External Pu...

Page 95: ...upply voltage for I O TBD All VCCIB4 AB21 AC22 AD23 AE23 T14 U15 U16 2 5 V supply voltage for I O TBD All VCCIB5 AB5 AC4 AD3 AE3 T12 U10 U11 3 3 V supply voltage for I O All VCCIB6 AA4 AB3 AC1 AC2 P10...

Page 96: ...Voltage 1 VCCPLB PLL Supply Voltage 1 VCCPLC PLL Supply Voltage 1 VCCPLD PLL Supply Voltage 1 VCCPLE PLL Supply Voltage 1 VCCPLF PLL Supply Voltage 1 VCOMPLA PLL Ground 1 VCOMPLB PLL Ground 1 VCOMPLC...

Page 97: ...P ECSS Space Engineering SpaceWire Protocols ECSS E ST 50 52C February 2010 RTAX RTAX S SL RadTolerant FPGAs 5172169 13 8 10 Revision 13 August 2010 Actel Corporation RT3PE Radiation Tolerant ProASIC3...

Page 98: ...ROUTER 10X RTAX 1 RTAX2000S SL LVTTL LVDS 1 CQ 352 EV E B RT SPW ROUTER 10X RTAX 1 RTAX2000S SL LVTTL LVDS 1 CGS 624 EV E B RT SPW ROUTER 10X RT3PE 1 RT3PE3000L LVTTL LVDS 1 CG 484 B RT SPW ROUTER 6X...

Page 99: ...arified how timeout period is related to register value 1 1 2011 June 2 3 Router configuration area memory map corrected 3 2 6 Port disable clarified 3 2 8 On chip memory handling clarified 3 2 8 1 Au...

Page 100: ...implicit nor explicit Information furnished by Aeroflex Gaisler AB is believed to be accurate and reliable However no responsibility is assumed by Aeroflex Gaisler AB for its use nor for any infringem...

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