AEROFLEX GAISLER
37
RT-SPW-ROUTER
Copyright Aeroflex Gaisler AB
June 2012, Version 1.2
3.5.6.1
APB slave interface
As mentioned above, the APB interface provides access to the user registers which are 32-bits in
width. The accesses to this interface are required to be aligned word accesses. The result is undefined
if this restriction is violated.
3.5.6.2
AHB master interface
The port contains a single master interface which is used by both the transmitter and receiver DMA
engines. The arbitration algorithm between the channels is done so that if the current owner requests
the interface again it will always acquire it. This will not lead to starvation problems since the DMA
engines always deassert their requests between accesses.
The AHB accesses can be of size byte, halfword and word (HSIZE = 0x000, 0x001, 0x010). Byte and
halfword accesses are always NONSEQ.
The burst length will be half the AHB FIFO size except for the last transfer for a packet which might
be smaller. Shorter accesses are also done during descriptor reads and status writes.
The AHB master also supports non-incrementing accesses where the address will be constant for sev-
eral consecutive accesses. HTRANS will always be NONSEQ in this case while for incrementing
accesses it is set to SEQ after the first access. This feature is included to support non-incrementing
reads and writes for RMAP.
If the core does not need the bus after a burst has finished there will be one wasted cycle (HTRANS =
IDLE).
BUSY transfer types are never requested and the port provides full support for ERROR, RETRY and
SPLIT responses.
3.5.6.3
Clocking
The AMBA ports run on the same clock as the router switch matrix.
3.5.7
Registers
The port is programmed through registers mapped into APB address space. The addresses in the table
below are offsets from each port’s base address. The actual AMBA AHB address used to access the
port is determined as follows: The AMBA ports’ registers are accessed through an APB interface
which resides on the APB bus. The APB bus is connected to the AHB bus using an APB controller
whose AHB address determines the first base address for the AMBA ports.
