AEROFLEX GAISLER
56
RT-SPW-ROUTER
Copyright Aeroflex Gaisler AB
June 2012, Version 1.2
3.8
Signal definitions and reset values
The signals and their reset values are described in table 49.
Table 49. Signal definitions and reset values
Signal name
Type
Function
Active
Reset value
spw_clk
Input
Transmitter default run-state clock
Rising edge
-
spw_rxdp[ ]
Input, LVDS
Data input, positive
1) 3)
High
-
spw_rxdn[ ]
Input, LVDS
Data input, negative
1) 3)
Low
-
spw_rxsp[ ]
Input, LVDS
Strobe input, positive
1) 3)
High
-
spw_rxsn[ ]
Input, LVDS
Strobe input, negative
1) 3)
Low
-
spw_txdp[ ]
Output, LVDS
Data output, positive
1) 3)
High
Logical 0
spw_txdn[ ]
Output, LVDS
Data output, negative
1) 3)
Low
Logical 1
spw_txsp[ ]
Output, LVDS
Strobe output, positive
1) 3)
High
Logical 0
spw_txsn[ ]
Output, LVDS
Strobe output, negative
1) 3)
Low
Logical 1
spw_rxd[ ]
Input, LVTTL
Data input, positive
2) 3)
High
-
spw_rxs[ ]
Input, LVTTL
Strobe input, positive
2) 3)
High
-
spw_txd[ ]
Output, LVTTL
Data output, positive
2
)
3)
High
Logical 0
spw_txs[ ]
Output LVTTL
Strobe output, positive
2) 3)
High
Logical 0
timecodeen
Input
Enable time-code functionality
High
tickin[ ]
Input
Tick input signals for FIFO interfaces
High
timeinn[7:0]
Input
Time input signals for FIFO interface n
-
tickout[ ]
Output
Tick output signals for FIFO interfaces
High
timeoutn[7:0]
Output
Time output signals for FIFO interface n
-
rxread[ ]
Input
Receiver FIFO read signals for FIFO interfaces
High
rxcharn[8:0]
Output
Receiver character signals for FIFO interface n
-
Logical 0
txwrite[ ]
Input
Transmitter FIFO write signals for FIFO interfaces
High
txcharn[8:0]
Input
Transmitter character signals for FIFO interface n
-
txfull[ ]
Output
Transmitter full signal for FIFO interfaces
High
Logical 0
txafull[ ]
Output
Transmitter almost full signal for FIFO interfaces
High
Logical 0
rxcharav[ ]
Output
Receiver data available signal for FIFO interfaces
High
Logical 0
rxaempty[ ]
Output
Receiver empty signal for FIFO interfaces
High
Logical 0
enbridge[ ]
Input
Enables bridge mode for the FIFO interfaces
High
