Advantech PCI-1240, User Manual

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PCI-1240/PCI-1240U User Manual 50
Table C.2: PCI-1240/PCI-1240U WRITE register format
Base Add. D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 W
Command Register: WR0
RESET U Z Y X
Axis Assignments Command Code
2 W
Mode Register 1: WR1
D-END C-STA C-ENDP
≥
C+ P < C+ P < C- P
≥
C- PULSE IN3-E IN3-L IN2-E IN2-L IN1-E IN1-L IN0-E IN0-L
Interrupt Enable/Disable Driving Stop Input Signal Enable/Disable
4 W
Mode Register 2: WR2
INP-E INP-L ALM-EALM-L PIND1 PIND0 PINMD DIR-L PLS-L PLSMDCMPSLHLMT- HLMT+ LMTMD SLMT- SLMT+
6 W
Mode Register 3: WR3
OUT7 OUT6 OUT5 OUT4 OUTSL EXOP1EXOP0 SACC DSNDE MANLD
8 W
Output Register: WR4
UOUT3UOUT2UOUT1UOUT0ZOUT3 ZOUT2 ZOUT1 ZOUT0 YOUT3YOUT2YOUT1YOUT0XOUT3XOUT2XOUT1XOUT0
A W
Interpolation Mode Register: WR5
BPINT CINT CMPLSEXPLS LSPD1 LSPD0 AX31 AX30 AX21 AX20 AX11 AX10
Interrupt Step Output Constant Vector Speed ax3 ax2 ax1
C W
Data Writing Register 1: WR6
WD15 WD14 WD13 WD12 WD11 WD10 WD9 WD8 WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
E W
Data Writing Register 2: WR7
WD31 WD30 WD29 WD28 WD27 WD26 WD25 WD24 WD23 WD22 WD21 WD20 WD19 WD18 WD17 WD16
10 W
Clear Interrupt Register: CLRINT
Clear Interrupt Register
14 W
Pulse Generator Mode Register: PGM
PGMU3PGMU2PGMU1PGMU0PGMZ3 PGMZ2 PGMZ1 PGMZ0PGMY3PGMY2PGMY1PGMY0PGMX3PGMX2PGMX1PCMX0