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28

 Operations

Leading

EDGE COMPUTING

PXI Star and PXIe differential star (PXIe_DSTARB). The trigger
decision sends a trigger signal to internal FPGA for acquisition
operation, as well as one of the PXI Trigger Bus bit for multi-mod-
ule synchronization operations.

3.3.1

Software Trigger

The software trigger, generated by software command, is asserted
immediately following execution of specified function calls to begin
the operation. 

3.3.2

External Digital Trigger

An external digital trigger is generated when a TTL signal rising
edge or falling edge is detected at the SMA connector TRG IN on
the front panel. As shown, trigger polarity can be selected by soft-
ware. Note that the signal level of the external digital trigger signal
should be TTL compatible, and the minimum pulse width 20 ns.

Figure 3-5: External Digital Trigger

 

Pulse Width > 20ns

Pulse Width > 20ns

Rising Edge Trigger Event

Falling Edge Trigger Event

Summary of Contents for PXIe-9834

Page 1: ...Leading EDGE COMPUTING PXIe 9834 4CH 16 bit 80MS s PXIe Digitizer User s Manual Manual Rev 1 0 Revision Date September 12 2019 Part No 50 17057 1000 ...

Page 2: ...ii Leading EDGE COMPUTING Revision History Revision Release Date Description of Change s 1 0 September 12 2019 Initial release ...

Page 3: ...l damages arising out of the use or inability to use the product or documentation even if advised of the possibility of such damages Environmental Responsibility ADLINK is committed to fulfill its social responsi bility to global environmental preservation through compliance with the European Union s Restriction of Hazardous Substances RoHS directive and Waste Electrical and Electronic Equipment W...

Page 4: ...and vinyl materials which are known to the State of California to cause cancer and acrylamide benzene cadmium lead mercury phthalates toluene DEHP DIDP DnHP DBP BBP PVC and vinyl materials which are known to the State of California to cause birth defects or other reproductive harm For more information go to www P65Warnings ca gov Trademarks Product names mentioned herein are used for identificatio...

Page 5: ...erly NOTE NOTE Additional information aids and tips that help users perform tasks CAUTION Information to prevent minor physical injury component dam age data loss and or program corruption when trying to com plete a task WARNING Information to prevent serious physical injury component damage data loss and or program corruption when trying to complete a specific task ...

Page 6: ...vi Preface Leading EDGE COMPUTING This page intentionally left blank ...

Page 7: ... 3 1 3 4 Crosstalk DC to 10MHz 3 1 3 5 Spectral Characteristics 4 1 3 6 Timebase 6 1 3 7 Triggers 7 1 3 8 Mechanical and Environmental 9 1 3 9 Power Consumption 9 1 4 Software Support 10 1 4 1 MAPS Core 11 1 4 2 MAPS LV LabVIEW Support 14 1 4 3 MAPS C C C Support 14 1 5 Device Layout and I O Connectors 15 2 Getting Started 19 2 1 Installation Environment 19 2 2 Package Contents 20 2 3 Installing t...

Page 8: ... PXI Star 30 3 3 6 PXIe Differential Trigger 30 3 4 Trigger Modes 31 3 4 1 Post Trigger Mode 31 3 4 2 Delayed Trigger Mode 32 3 4 3 Pre Trigger Mode 32 3 4 4 Middle Trigger Mode 33 3 4 5 Acquisition with Re Triggering 34 3 5 Timebase 35 3 5 1 Internal Sampling Clock 35 3 5 3 External Reference Clock 36 3 6 Acquisition Timing Control 37 3 7 Synchronizing Multiple Modules 39 3 7 1 Multi module Synch...

Page 9: ... 27 Figure 3 5 External Digital Trigger 28 Figure 3 6 Analog Trigger Conditions 29 Figure 3 7 Post Trigger Acquisition 31 Figure 3 8 Delayed Trigger Mode Acquisition 32 Figure 3 9 Pre Trigger Mode Acquisition 32 Figure 3 10 Middle Trigger Mode Acquisition 33 Figure 3 11 Re Trigger Mode Acquisition 34 Figure 3 12 Timebase Architecture 35 Figure 3 13 Varying Sampling Rates via Scan Interval Counter ...

Page 10: ...x List of Figures Leading EDGE COMPUTING This page intentionally left blank ...

Page 11: ...cifications 6 Table 1 8 External Reference Clock 7 Table 1 9 Triggers 7 Table 1 10 External Digital Trigger Input 8 Table 1 11 Onboard Reference Calibration 8 Table 1 12 Specifications 9 Table 1 13 Power Consumption 9 Table 1 14 PXIe 9834 I O Array Legend 17 Table 3 1 Input Range and Data Format 24 Table 3 2 Input Range FSR and FSR Values 25 Table 3 3 Input Range Midscale Values 25 Table 3 4 Count...

Page 12: ...xii List of Tables Leading EDGE COMPUTING This page intentionally left blank ...

Page 13: ...accurate signal acquisition Providing extremely large onboard memory the PCI Express 4 lane interface supports data stream ing even at the highest sampling rates The PXIe 9834 is also auto calibrated with an onboard reference circuit compensating the offset and gain error of acquired analog input signals The PXIe 9834 is accordingly ideal for applications such as radar signal acquisition fiber opt...

Page 14: ...alog Input Channel Characteristics Item Specification Comment Channels 4 single ended Connector type SMA Input coupling DC or AC software selectable ADC resolution 16 Bit Input range 0 5 V 1 V 5V or 10V 10V range support only for 1MΩ input impedance Bandwidth 3dB 40MHz Maximum input overload 7Vrms For 50Ω 0 5V or 1V or 5V input range 10V For 1MΩ 0 5V or 1V 30V For 1MΩ 5V or 10V Input impedance 50Ω...

Page 15: ...to 10MHz Input Range Offset Error Gain Error 50Ω Input Impedance 1MΩ Input Impedance 0 5V 0 8mV 0 8mV 0 6 1V 0 8mV 1 2mV 5V 1 5mV 4 0mV 10V N A 8mV Input Range System Noise 0 5V 0 1mVrms 1V 0 15mVrms 5V 1mVrms 10V 1 5mVrms Input Range Crosstalk Comment 0 5V 80dB 1MHz sine wave 90 of full scale range 1V 5V 10V 90dB 1MHz sine wave 90 of full scale range ...

Page 16: ... Characteristics Figure 1 1 Typical Frequency Response 1MΩ input impedance Index Specification Comment SINAD 68dB 0 5V 1V 5V 65dB 10V THD 78dB For all ranges SFDR 78dB For all ranges SNR 69dB 0 5V 1V 5V 65dB 10V NOTE NOTE Values reflect 50Ω and 1MΩ input impedance with digital filter off ...

Page 17: ...Introduction 5 PXIe 9834 Figure 1 2 Typical Frequency Response 50Ω input impedance ...

Page 18: ...nt panel SMA connector External reference clock CLK IN front panel SMA con nector PXI_10M PXIe backplane 10MHz refer ence clock The reference clock supplies an onboard PLL circuit and generates 80MHz for ADC Sampling clock frequency Internal 80MS s maximum ranges from 1 22KS s to 80MS s 1 22kS s to 80MS s External reference clock 10MHz Internal onboard oscillator accuracy 25ppm ...

Page 19: ...cycle tolerance 45 to 55 Reference clock frequency range 10MHz 2KHz Trigger Source Mode Trigger source Internal software trigger External X External digital trigger from TRG IN front panel X Analog trigger from any of analog input channels X PXI Trigger Bus 0 7 X PXI STAR Trigger X PXIe_DSTARB Trigger modes X Post trigger X Delay trigger X Pre trigger X Middle trigger X Re trigger for post trigger...

Page 20: ...ctor Compatibility 3 3 V TTL 5 V tolerant Input high threshold VIH 2 0 V Input low threshold VIL 0 8 V Maximum input overload 0 5 V to 5 5 V Trigger polarity Rising or falling software selectable Trigger pulse width 20 ns minimum Onboard Reference Calibration Calibration Specification Onboard reference 1 8V 0 9V 0 45V Temperature coefficient 5 0 ppm C Warm up time 15 minutes recommended ...

Page 21: ...Gen1 Operating Conditions Temperature 0 C to 50 C Relative humidity 5 to 95 non condensing Storage Conditions Temperature 20 C to 80 C Relative humidity 5 to 95 non condensing Compliance Certification X EN 55032 2015 AC 2016 Class B X EN 55024 2010 A1 2015 Immunity X EN61326 1 2 Class B X FCC 47 CFR Part 15B Class B X ICES 003 Issue 6 2016 Class B X ANSI C63 4 2014 Class B Power Rail Standby Maxim...

Page 22: ...protected with licensing codes Without the code you may install and run the demo version for trial demonstration purposes for only up to two hours Contact your ADLINK dealer to purchase the soft ware license The ADLINK Measurement Automation Platform Service MAPS is a software service package designed for data acquisition automation and PXI platform By leveraging the sophisticated architecture in ...

Page 23: ...nnection Explorer With MAPS Core installed in a user provided PC the operating system can identify ADLINK s devices correctly and assign necessary resources for low level access such as IO read write or direct memory access MAPS Core is necessary for all ADLINK DAQ modules To ensure the user has the latest software go to the ADLINK product web page or contact ADLINK technical service ...

Page 24: ...ed ADLINK Connection Explorer ACE Through ACE users can dis cover and manage ADLINK DAQ modules For example the user can reserve a certain size of memory buffer for DMA operation or set the user alias name for operating the module in a LabVIEW environment Figure 1 4 ADLINK Connection Explorer ACE ...

Page 25: ...soft front panel for digitizer products By clicking the Launch but ton in the lowest Utility block this soft front panel allows users to control digitizers through the UI and display the acquired wave form data on the screen Figure 1 5 The ADLINK Connection Explorer ACE Soft Front Panel ...

Page 26: ... following website and refer to the MAPS LV manual https www adlinktech com Products Data _Acquisition DAQSoftware_Utility MAPS_LV Lang en 1 4 3 MAPS C C C Support For customers who develop their own programs in C or C envi ronments install the MAPS C software package MAPS C includes all the software components required for developing applications in C C such as header files device API library and...

Page 27: ...Introduction 15 PXIe 9834 1 5 Device Layout and I O Connectors All dimensions are in mm Figure 1 6 PXIe 9834 Dimensions ...

Page 28: ...16 Introduction Leading EDGE COMPUTING The PXIe 9834 I O array is labeled to indicate connectivity as shown All I O connectors are SMA Figure 1 7 PXIe 9834 Front Panel CH0 CH1 CH2 CH3 CLK IN TRG IN ...

Page 29: ...bel Comment Analog CH0 Analog Input Channel Analog CH1 Analog CH2 Analog CH3 reference clock CLK IN Input for reference clock to the digitizer External Digital Trigger TRG IN External digital trigger input receiving trigger signal from external instrument thus initiating acquisition ...

Page 30: ...18 Introduction Leading EDGE COMPUTING This page intentionally left blank ...

Page 31: ... flat and cross head screwdrivers preferably with magnetic heads as screws and standoffs are small and easily misplaced Recommended Installation Tools X Phillips cross head screwdriver X Flat head screwdriver X Anti static wrist strap X Antistatic mat The ADLINK PXIe 9834 is electrostatically sensitive and can be easily damaged by static electricity The module must be handled on a grounded anti st...

Page 32: ...ntact the dealer CAUTION The equipment must be protected from static discharge and physical shock Never remove any of the socketed parts except at a static free workstation Use the anti static bag shipped with the product to handle the equipment and wear a grounded wrist strap when servicing WARNING Do not install or apply power to equipment that is damaged or missing components Retain the shippin...

Page 33: ...e mod ule into the chassis 5 Once the module is fully seated a click can be heard from the ejector latch 6 Tighten the screw on the faceplate 7 Power up the PXIe system chassis NOTE NOTE The power cable provides grounding to prevent hazardous ESD electrostatic discharge WARNING Do not to perform hot swapping replacement disconnecting or connecting of any components including cards and cabling on c...

Page 34: ...22 Getting Started Leading EDGE COMPUTING This page intentionally left blank ...

Page 35: ...e PXIe 9834 s 50Ω or 1MΩ input impedance circuit along with AC DC coupling makes it easy to acquire a wide variety of signals Sophisticated attenuation circuit design offers several XJ4 FPGA DDR3 CH0 CH1 CH2 CH3 CLK IN TRG IN System Power XJ3 TNB Analog Front End TNB TNB TNB TNB System Clock TNB Trigger Buffer Calibration ADC ADC ADC ADC PXI Instrumentation Signals PCI Express Quad ADC 16 Bits FPG...

Page 36: ...re them in digital data with all designs applied to four analog input channels independently For auto calibration an elaborate onboard reference circuit provides stable and low drift voltage of particular benefit when ever auto calibration is executed in response to environmental temperature change For more details about auto calibration please see Calibration on page 45 3 2 2 Input Range and Data...

Page 37: ...igger signals through PXI_STAR and PXIe differential star triggers The 8 bit parallel PXI Trigger bus provides additional channels to transmit and receive triggers between peripheral slots The PXIe chassis further provides 10MHz PXI_CLK10 clock options distributed to each peripheral slot with minimal clock skew Input Range Least Significant Bit FSR 1LSB FSR Bipolar Analog Input 10 0V 0 305 mV 9 99...

Page 38: ...he AD trigger condition is met the data will be transferred to the system memory by the bus mastering DMA In a multi user or multi tasking OS such as Microsoft Windows Linux or other it is difficult to allocate a large continuous memory block Therefore the bus controller provides DMA transfer with scatter gather function to link non contiguous memory blocks into a linked list so users can transfer...

Page 39: ... trigger sources The PXIe 9834 supports internal software trigger external digital trigger analog trigger from AI CH0 to CH3 PXI Trigger Bus 0 7 Local Memory FIFO PCI Express Bus First PCI Address First Dual Address Transfer Size Next Descriptor PCI Address Dual Address Transfer Size Next Descriptor PCI Address Dual Address Transfer Size Next Descriptor MUX Software Trigger External Digital Trigge...

Page 40: ...ely following execution of specified function calls to begin the operation 3 3 2 External Digital Trigger An external digital trigger is generated when a TTL signal rising edge or falling edge is detected at the SMA connector TRG IN on the front panel As shown trigger polarity can be selected by soft ware Note that the signal level of the external digital trigger signal should be TTL compatible an...

Page 41: ... event occurs when the analog input signal changes from a voltage lower than the specified trigger level to one higher than the specified trigger level Falling Edge Trigger This trigger event occurs when the analog input signal changes from a voltage higher than the specified trigger level to one lower than the specified trigger level Figure 3 6 Analog Trigger Conditions Trigger Level Analog Signa...

Page 42: ...ected as trigger source the PXIe 9834 can accept a TTL compatible digital signal as a trigger signal The trig ger occurs when a rising edge or falling edge is detected at PXI STAR This utility can configure the trigger polarity The minimum pulse width requirement of this digital trigger signal is 20ns 3 3 6 PXIe Differential Trigger PXIe 9834 also features a trigger source from PXIe differential t...

Page 43: ...on is applicable when data is to be collected after the trigger event as shown When the operation starts PXIe 9834 waits for a trigger event Once the trigger signal is received acquisition begins Data is generated from ADC and transferred to system memory continuously The acquisition stops once the total data amount reaches a predefined value Figure 3 7 Post Trigger Acquisition Operation Start Tri...

Page 44: ...ng once specified func tion calls are executed to begin the pre trigger operation and stopping when the trigger event occurs If the trigger event occurs after the specified amount of data has been acquired the system stores only data preceding the trigger event by a specified amount as follows Figure 3 9 Pre Trigger Mode Acquisition Operation Start Trigger Event Occurs Acquisition Stop Time N Samp...

Page 45: ...r the trigger event with the amount to be collected set individually M and N samples as follows Figure 3 10 Middle Trigger Mode Acquisition Time Operation start Acquisition start Trigger Data Acquisition stop Data transfer to system begins N samples M samples Trigger event occurs ...

Page 46: ... modes with different limitations on the spacing between trigger events in each mode Trigger events arriving too close to the previous instance will be ignored by the digitizer X In Post Trigger mode the minimum spacing between trigger events is N 1 X In Delayed Trigger mode the minimum spacing between trigger events is N D 1 where D is the number of the delayed setting X If R is set to zero it me...

Page 47: ...base Figure 3 12 Timebase Architecture 3 5 1 Internal Sampling Clock The PXIe 9834 internal 80MHz crystal oscillator acts as a sam pling clock for ADC MUX Phase Lock Loop Onboard Oscillator PXI_CLK10 MUX ADC 0 Buffer ADC 1 ADC 2 ADC 3 ...

Page 48: ... is needed By software command the CLK IN will route external 10MHz clock to the PLL synthesizer and generate a precise 80MHz clock for ADC As an added benefit from the PXIe platform the chassis also pro vides reference 10MHz clock to each peripheral PXIe slot The PXIe 9834 also routes this 10MHz to internal PLL circuit enabling synchronization of multiple PXIe 9834 modules in a single chassis wit...

Page 49: ...hen a trigger is accepted by the digitizer the acquisi tion engine commences acquisition of data from ADC and stores the sampled data to onboard memory When onboard memory is not empty data will be transferred to system memory automati cally via the DMA Direct Memory Access engine The sampled data is generated continuously at the rising edge of timebase according to the scan interval counter ScanI...

Page 50: ...Comment ScanIntrv Scan Interval Counter 16 bit 1 65535 Timebase divider to achieve equivalent sampling rate of the digitizer when sampling rate timebase ScanIntrv DataCnt Data Counter 31 bit 1 2147483647 Specifies the amount of data to be acquired invalid when double buffer mode infinite data number is selected for continuous data sampling trigDelayTicks Delay Trigger Counter 16 bit 1 65535 Indica...

Page 51: ...and timebase synchronization Trigger synchronization implements a signal that initiates acquisi tion and timebase synchronization provides the fundamental clock for AD operation As shown in the following two digitizer modules operating at diverse onboard clock and trigger signals free run result in not only trigger time difference but also clock phase error Figure 3 14 Non synched Digitizer Module...

Page 52: ...ith required buffering of trigger and timebase signals and equal wiring length between the function generator and digitizers trigger and timebase synchronization are possible In this scenario the function generator is a master device that out puts trigger and timebase and the two digitizers are slave devices sharing the same trigger and timebase Figure 3 15 External Instrument Synchronization Sine...

Page 53: ...s as a master device and transmits trigger timebase to the two slave digitizers Figure 3 16 Module based Synchronization In the scenarios described trigger and timebase signal buffering is required with one or multiple signal buffering modules necessary Digitizer 2 CLK IN TRG IN CLK 1 ADC ADC ADC ADC Digitizer Controller Trigger Decision Digitizer Module 1 TRG 1 CLK OUT TRG OUT Digitizer 3 CLK IN ...

Page 54: ...tesy of PXI Express Specification Tutorial pdf from PXI System Alliance website www pxisa org Figure 3 17 PXIe Instrumentation Signals In the PXIe chassis a system timing slot distributes trigger signals through PXI_STAR and PXIe differential star triggers The 8 bit parallel PXI Trigger Bus provides additional channels for transmit ting and receiving triggers between peripheral slots The PXIe chas...

Page 55: ...is on the front panel and the PXI Trigger Bus PXI_STAR and PXIe_DSTARB are from the PXIe chassis When the PXIe 9834 acts as a master device its trigger signal is output to one bit of the PXI Trigger Bus as determined by software selec tion Figure 3 18 Trigger Architecture MUX Software Trigger External Digital Trigger Analog Trigger PXI Trigger Bus PXI_STAR PXIe_DSTARB Trigger Decision To internal ...

Page 56: ...ation the PXIe 9834 acts as a slave device receiving 10MHz reference clock from the front panel CLK IN or PXI_CLK10 from the PXIe chassis Figure 3 19 PXI_CLK10 as 10MHz Reference MUX Phase Lock Loop Onboard Oscillator PXI_CLK10 MUX ADC 0 Buffer ADC 1 ADC 2 ADC 3 ...

Page 57: ...he default bank records the factory cali brated constants providing written protection preventing erroneous auto calibration Bank 1 is user defined space pro vided for storage of self calibration constants Upon execution of auto calibration the calibration constants are recorded to Bank 1 When PXIe 9834 boots the driver accesses the calibration con stants and is automatically set to hardware In th...

Page 58: ...ference to ensure the accuracy of auto calibration The reference voltage is mea sured on the production line and recorded in the on board EEPROM Before initializing auto calibration it is recommended to warm up the PXIe 9834 for at least 20 minutes and remove connected cables Figure A 1 Auto Calibration Block Diagram NOTE NOTE It is not necessary to manually factor delay into applications as the P...

Page 59: ... Capture data and calculate offset compensation parameters Are all channels and all ranges complete No Set calibration source to calibration voltage Capture data and calculate gain compensation parameters Yes Are all channels and all ranges complete No Yes Set analog front end input to SMB connector Auto calibration start Auto calibration complete ...

Page 60: ...48 Calibration Leading EDGE COMPUTING This page intentionally left blank ...

Page 61: ...emperature of 50ºC X When installing mounting or uninstalling removing device or when removal of a chassis cover is required for user servicing Z Turn off power and unplug any power cords cables Z Reinstall all chassis covers before restoring power X To avoid electrical shock and or damage to device Z Keep device away from water or liquid sources Z Keep device away from high heat or humidity Z Kee...

Page 62: ...gns of breakage X Disconnect the power supply cord before loosening the thumbscrews and always fasten the thumbscrews with a screwdriver before starting the system up X It is recommended that the device be installed only in a server room or computer room where access is Z Restricted to qualified service personnel or users familiar with restrictions applied to the location reasons therefor and any ...

Page 63: ...ing this surface could result in bodily injury To reduce risk allow the surface to cool before touching RISQUE DE BRÛLURES Ne touchez pas cette surface cela pourrait entraîner des blessures Pour éviter tout danger laissez la surface refroidir avant de la toucher ...

Page 64: ...52 Important Safety Instructions Leading EDGE COMPUTING This page intentionally left blank ...

Page 65: ... 408 360 0200 Toll Free 1 800 966 5200 USA only Fax 1 408 360 0222 Email info adlinktech com ADLINK Technology China Co Ltd 300 Fang Chun Rd Zhangjiang Hi Tech Park Pudong New Area Shanghai 201203 China Tel 86 21 5132 8988 Fax 86 21 5132 3588 Email market adlinktech com ADLINK Technology GmbH Hans Thoma Straße 11 D 68163 Mannheim Germany Tel 49 621 43214 0 Fax 49 621 43214 30 Email emea adlinktech...

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