ADLINK Technology PXIe-9834, User Manual, Page: 37 / 65

Operations 25
PXIe-9834
The following table shows the represented digital code when input
voltage is at negative full scale and positive full scale. Since the
data format for the PXIe-9834 is 2’s complement, the most signifi-
cant bit represents the sign of input voltage.
Table 3-2: Input Range FSR and -FSR Values
The following table shows the digital code when input voltage is
roughly midscale, approximately 0 V.
Table 3-3: Input Range Midscale Values
In the PXIe chassis, a system timing slot distributes trigger signals
through PXI_STAR and PXIe differential star triggers. The 8-bit
parallel PXI Trigger bus provides additional channels to transmit
and receive triggers between peripheral slots. The PXIe chassis
further provides 10MHz (PXI_CLK10) clock options distributed to
each peripheral slot with minimal clock skew.
Input Range
Least Significant
Bit
FSR-1LSB -FSR
Bipolar
Analog Input
± 10.0V 0.305 mV 9.999694824 -10V
± 5.0V 0.153 mV 4.999847412 -5V
± 1.0V 0.031 mV 0.999969482 -1V
± 0.5V 0.015 mV 0.499984741 -0.5V
Digital Code N/A N/A 7FFF 8000
Mi1LSB Midscale Midscale -1LSB
Bipolar Analog
Input
0.305 mV 0 V -0.305 mV
0.153 mV 0 V -0.153 mV
0.031 mV 0 V -0.031 mV
0.015 mV 0 V -0.015 mV
Digital Code 0001 0000 FFFF