ADLINK Technology PXIe-9834, User Manual, Page: 38 / 65

26 Operations
Leading
EDGE COMPUTING
3.2.3 DMA Data Transfer
The PXIe-9834, a PXIe Gen 1 X 4 device, is equipped with four
80MS/s high sampling rate ADCs, generating a 640 MByte/second
rate.
To provide efficient data transfer, a PCI bus-mastering DMA is
essential for continuous data streaming, as it helps to achieve full
potential PCI Express bus bandwidth. The bus-mastering control-
ler releases the burden on the host CPU since data is directly
transferred to the host memory without intervention. Once analog
input operation begins, the DMA returns control of the program.
During DMA transfer, the hardware temporarily stores acquired
data in the onboard AD Data FIFO, and then transfers the data to
a user-defined DMA buffer in the computer.
Using a high-level programming library for high speed DMA data
acquisition, the sampling period and the number of conversions
needs simply to be assigned into specified counters. After the AD
trigger condition is met, the data will be transferred to the system
memory by the bus-mastering DMA.
In a multi-user or multi-tasking OS, such as Microsoft Windows,
Linux, or other, it is difficult to allocate a large continuous memory
block. Therefore, the bus controller provides DMA transfer with
scatter-gather function to link non-contiguous memory blocks into
a linked list so users can transfer large amounts of data without
being limited by memory limitations. In non-scatter-gather mode,
the maximum DMA data transfer size is 2 MB double words (8 MB
bytes); in scatter-gather mode, there is no limitation on DMA data
transfer size except the physical storage capacity of the system.
Users can also link descriptor nodes circularly to achieve a multi-
buffered DMA. Figure 3-3 illustrates a linked list comprising three
DMA descriptors. Each descriptor contains a PCI address, PCI
dual address, a transfer size, and the pointer to the next descrip-
tor. PCI address and PCI dual address support 64-bit addresses
which can be mapped into more than 4 GB of address space, but
the subsequent descriptor address must be less than 4GB.