22
•
Registers Format
4.9 FIFO Control Register
This register is used to control the on-board FIFO memory.
Address: BASE + 18h
Attribute:
write
Data Format:
Bit
7
6
5
4
3
2
1
0
BASE+18h
---
---
---
---
---
---
CLRTRG CLRFIFO
BASE+19h
---
---
---
---
---
---
---
---
BASE+1Ah
---
---
---
---
---
---
---
---
BASE+1Bh
---
---
---
---
---
---
---
---
bit 0 -- CLRFIFO, clear the on-board FIFO
When a "1" is written to this bit, the entire on-board FIFO is
cleared.
bit 1 -- CLRTRG, clear trigger detection flag
When a "1" is written to this bit, the trigger detection bit is
cleared.
bit 2..31 -- don't care
4.10 Acquisition Enable Register
The register enables or disables the ADC acquisition.
Address: BASE + 1ch
Attribute: write only
Data Format:
Bit
7
6
5
4
3
2
1
0
BASE+18h
---
---
---
---
---
---
---
ACQEN
BASE+19h
---
---
---
---
---
---
---
---
BASE+1Ah
---
---
---
---
---
---
---
---
BASE+1Bh
---
---
---
---
---
---
---
---
bit 31..1 -- don't care
bit 0 -- ACQEN, acquisition enable
When a "1" is written to this bit, the PCI-9812/10 is
ready to sample data. When a "0" is written, the PCI-
9812/10 is disabled.
Summary of Contents for NuDAQ PCI-9812/10
Page 1: ...NuDAQ PCI 9812 10 20MHz Simultaneous 4 CH Analog Input Card Users Guide ...
Page 4: ......
Page 57: ...C C Library 49 ...
Page 61: ...Calibration 53 ...
Page 69: ...Software Utility 61 ...
