ADLINK Technology NuDAQ PCI-9812/10, User Manual

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Operation Theorem
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5.3 A/D Trigger Source Control
Performing the trigger acquisition in PCI-9812/10, the following
items have to be specified before DMA operation starts:
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clock source : refer to section 5.4
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clock rate: refer to section 5.4
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trigger source: refer to section 5.3.1.
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trigger level: The trigger event occurs when the trigger
signal crosses the specified trigger voltage. Please refer to
section 4.5 for the relationship between the 8 -bit trigger
level and the trigger voltage.
The trigger is detected while the trigger event occurs. For Post-
trigger and Middle-trigger, the data acquisition is performed after the
trigger event; however, the time when the AD conversion starts is
350 ns slower than the time when th e trigger is detected. This
350ns delay will have minor effect for high speed data acquisition.
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trigger polarity: trigger slope. This ‘0’ value means positive
trigger and the ‘1’ value means negative trigger.
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trigger mode: refer to section 5.3.2.
5.3.1 Trigger Sources
Internal Trigger
An internal trigger is a software trigger. The trigger event occurs
when you call _9812_AD_DMA_Start( ) function to start the
operation.
External Analog Trigger
You can use the signal on any analog input channel (CH0, CH1,
CH2, or CH3) as the trigger signal for external analog trigger. The
trigger conditions for analog triggers are described as follows:
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Positive-slope trigger - The trigger event occurs the first
time the trigger signal (analog input signal) changes from a
voltage that is lower than the specified trigger level to a
voltage that is higher than the specified trigger level.
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Negative-slope trigger - the trigger event occurs the first
time the trigger signal (analog input signal) changes from a
voltage that is higher then the specified trigger level to a
voltage that is lower than the specified trigger level.