16
•
Registers Format
4.3 ADC Clock Divisor Register
The ADC sampling clock is generated by feeding the ADC source
clock to a clock frequency divider, the output of the frequency
divider becomes the sampling clock. The frequency of the ADC
sampling clock is:
Frequency of source clock / ADC clock divisor
Address: BASE + 04h
Attribute:
write only
Data Format:
Bit
7
6
5
4
3
2
1
0
Base + 4
DIV7
DIV6
DIV5
DIV4
DIV3
DIV2
DIV1
DIV0
Base + 5 DIV15 DIV14
DIV13 DIV12 DIV11 DIV10
DIV9
DIV8
Base + 6
---
---
---
---
---
---
---
---
Base + 7
---
---
---
---
---
---
---
---
DIV15..0: The AD clock frequency devisor
--- : don’t care
Note:
the minimum value of this register is 2, and the DIV0 is
hardwired to 0.
Summary of Contents for NuDAQ PCI-9812/10
Page 1: ...NuDAQ PCI 9812 10 20MHz Simultaneous 4 CH Analog Input Card Users Guide ...
Page 4: ......
Page 57: ...C C Library 49 ...
Page 61: ...Calibration 53 ...
Page 69: ...Software Utility 61 ...
