ADLINK Technology cPCI-6810, User Manual

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Introduction 11
Power Ramp Circuitry
The cPCI-6810/6820 features a power controller with power ramp
circuitry to allow the board's voltages to be ramped in a controlled
fashion. The power ramp circuitry eliminates any large voltage or
current spikes caused by hot-swap boards. This controlled
ramping is a requirement of the CompactPCI hot-swap
specification, PICMG 2.1, Version 1.0. The cPCI-6810/6810's
power controller unconditionally resets the board when it detects
that the 3.3V, 5V, and 12V supplies are below an acceptable
operating limit. These limits are defined as 4.75V (5V supply),
3.0V (3.3V supply), and 10.0V (+12V supply).
PCI Mezzanine Card (PMC) Interface
The cPCI-6810/6820 supports up to two PMC expansion slots
(only one slot on cPCI-6820). The PMC supports 3.3V PCI
environment and operates at up to 64bit/66MHz. The PMC
expansion card is on the secondary PCI bus of CNB30LE, i.e., it is
on PCI bus 1. Table 1-2 illustrates PMC availability depending on
the cPCI-6810/6820 model.
Watchdog Timer
The cPCI-6810/6820 implements a watchdog timer embedded in
the NS PC87417. The watchdog timer is an 8-bit down counter
with 1-minute resolution. Programmable I/O ports 10h - 12h of
bank 3 are used to configure the watchdog timer. The 8-bit timer is
programmable from 1 - 255 minutes. Once a value is set to the
WDT, the timer begins to count down. Any movement of keyboard,
mouse or software will reset the value and reload the timer again.
cPCI-6810 cPCI-6820
AA AB AC AD AE
PMC 1 (with rear I/O) Yes No Yes No No
PMC 2 Yes Yes No No No
2.5” HDD No Yes No Yes No
Table 1-2: PMC Options