52
Utilities
Offset 68H: WDT Lock Register
Bit 2 is used to choose the functionality of the timer. (0 =
Watchdog Timer mode, 1 = Free running mode) The free run-
ning mode ignores the first stage and only uses Preload Value
2. In free running mode it is not necessary to reload the timer
as it is done automatically every time the down counter
reaches zero.
Bit 1 enables or disables the WDT. (0 = Disabled, 1 = Enabled)
Bit 0 will lock the values of this register until a hard reset occurs
or power is cycled. (0 = unlocked, 1 = locked) The default is
Unlocked.
GPIO Control Registers
There are three GPIOs on the cPCI-3840 related to the watchdog
timer. They are listed as follows. The GPIO control base port is
480H.
WDT_TOUT# pin selection
The WDT_TOUT# signal is multiplexed with GPIO32. When
using WDT, this signal must be switched to WDT_TOUT# func-
tion. It uses bit 0 of GP 30H to set WDT_TOUT func-
tion. (0 = WDT_TOUT#, 1 = GPIO32)
RESET hardware circuit selection
GPO24 of the 6300ESB is designed to control the reset circuit.
When GPO24 is low, the system will reset according to the
level of the WDT_TOUT# signal. When GPO24 is high, the
system will not be reset by WDT_TOUT#. Set bit 24 of GPIO-
BASE + 04H to 0 for output use. Bit 24 of GP 0CH
determines the level of GPO24. (0 = Low, 1 = High) There
already exists a setting in BIOS setup menu. (Integrated
Peripherals page) The user can set this item before program-
ming WDT.
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