ADLINK Technology CoreModule 730 Reference Manual Download

Page: 10 / 36

Chapter 2

Product Overview

Reference Manual

CoreModule 730

Block Diagram

Figure 2-2

shows the functional components of the CoreModule 730.

Figure 2-2. Block Diagram

LPC

H8S Controller

(LPC to SPI
Conversion

and Power

Management)

USB0 and USB1

Header

USB2 and USB3

Header

Ethernet

Controller

Ethernet

Magnetics

Gigabit
Ethernet

Header

CK540

Clock

CPU

Temperature

Sensor

SUMIT

Connector - B

SUMIT

Connector - A

DDR2

SODIMM

(up to 2GB)

Intel

US15W

SCH

Intel Atom

Z530

CPU

GPIO

Header

FSB

USB

VGA

Header

LVDS Header

Compact Flash

Socket

IDE

Header

SDVO to RGB

Controller

I2C to SUMIT

SPI to SUMIT

X1 PCIe

X2 PCIe

X1 PCIe

PCIe to PCIe

Switch

SMBus

Header

CM730blkdiag_b

Summary of Contents for CoreModule 730

Page 1: ...CoreModuleTM 730 Stackable Single Board Computer Reference Manual P N 50 1Z019 1000 ...

Page 2: ...n later in this section Audience This manual provides reference only for computer design engineers including but not limited to hardware and software designers and applications engineers ADLINK Technology Inc assumes you are qualified to design and implement prototype computer equipment ii Reference Manual CoreModule 730 TRADEMARKS CoreModule and the Ampro logo are registered trademarks and ADLINK...

Page 3: ...ons 12 Power Specifications 13 Environmental Specifications 13 Thermal Cooling Requirements 13 Chapter 3 Hardware 15 Overview 15 CPU 16 Graphics 16 Memory 16 Interrupt Channel Assignments 16 Memory Map 17 I O Address Map 18 USB Interfaces 19 Ethernet Interface 20 Video Interfaces 21 VGA Interface 21 LVDS Interface 22 Utility Interface 23 Power Button 23 Reset Switch 23 BIOS Recovery Using Reset Sw...

Page 4: ...ocket Descriptions 9 Table 2 3 Jumper Settings 11 Table 2 4 Weight and Footprint Dimensions 12 Table 2 5 Power Supply Requirements 13 Table 2 6 Environmental Requirements 13 Table 3 1 Interrupt Channel Assignments 16 Table 3 2 Memory Map 17 Table 3 3 I O Address Map 18 Table 3 4 USB0 and USB1 Interface Pin Signals J12 19 Table 3 5 USB2 and USB3 Interface Pin Signals J13 20 Table 3 6 Ethernet Inter...

Page 5: ...essfully Some of these references are also available on the ADLINK s InfoCenter web page The InfoCenter was created for embedded system developers to share ADLINK s knowledge insight and expertise Specifications SUMIT Specification Revision 1 0 April 4 2008 Web site http www sff sig org sumit_spec_v10 pdf ISM Specification Revision 1 0 June 2008 Web site http www sff sig org ism_spec_v10 pdf PCI 2...

Page 6: ...uct_briefs Product_Brief_PEX8505_v1_2_11Apr08 pdf Intel Corporation and the 82574IT Gigabit Ethernet controller Web site http download intel com design network datashts 82574 pdf NOTE If you are unable to locate the datasheets using the links provided search the internet to find the manufacturer s web site and locate the documents you need ...

Page 7: ...igital I O interfaces Stackable expansion modules can be stacked with the CoreModule 730 avoiding the need for card cages and backplanes The stackable expansion modules can be mounted directly to the SUMIT connector of the CoreModule 730 SUMIT compliant modules can be stacked with an inter board spacing of 0 60 15mm so that a 3 module system fits in a 3 6 x 3 8 x 2 4 space See Figure 2 1 One or mo...

Page 8: ...eModule 730 stacks with ADLINK MiniModule products or other SUMIT compliant expansion boards or it can serve as the computing engine in a fully customized application Module Features CPU Provides x86 based Intel Atom Z530 1 60GHz microprocessor Supports a Front Side Bus FSB of 400 533 MHz Supports IA 32 bit architecture Provides 32kB Unified Instruction Cache and 24kB Write Back Data Cache Provide...

Page 9: ...ode supports enhanced proprietary collision reduction mode Utility Interface Supports standard external 8Ω Beep speaker interface Supports external Reset switch Supports external Power button USB Ports Provide three root USB hubs Provide seven USB ports Support USB v2 0 EHCI and v1 1 UHCI Video LCD CRT Display Supports full hardware acceleration of H 264 video decode standard Supports CRT 2048 x 1...

Page 10: ...nd USB1 Header USB2 and USB3 Header Ethernet Controller Ethernet Magnetics Gigabit Ethernet Header CK540 Clock CPU Temperature Sensor SUMIT Connector B SUMIT Connector A DDR2 SODIMM up to 2GB Intel US15W SCH Intel Atom Z530 CPU GPIO Header FSB USB VGA Header LVDS Header Compact Flash Socket IDE Header SDVO to RGB Controller I2C to SUMIT SPI to SUMIT X1 PCIe X1 PCIe X1 PCIe X2 PCIe X1 PCIe PCIe to ...

Page 11: ...32 bit processor offered at 1 6 GHz Embedded CPU Sensor U2 Analog Devices ADM1032ARMZ 1 CPU Temperature Monitor Temperature Monitor and Alarm SCH U3 Intel US15W Graphics Memory and I O Expansion controller System Controller Hub Converter U4 Chrontel CH7317A SDVO to RGB Display Controller Digital to Analog Conversion Switch U10 PLX PEX8505 PCIe to PCIe Switch I O Expansion Interconnect Controller U...

Page 12: ...Chapter 2 Product Overview 8 Reference Manual CoreModule 730 Figure 2 3 Component Locations Front View U1 U3 U4 U42 U10 CM730_comp_front_b U2 ...

Page 13: ...net Front 10 pin 0 079 2mm right angle header for 10 100 1000BaseT Gigabit Ethernet port J5 SUMIT A Front 52 pin 0 025 0 635mm connector for out going USB PCIe Power ACPI SMBus I2C SPI LPC Serial Keyboard Mouse and Clock signals J6 SUMIT B Front 52 pin 0 025 0 635mm connector for PCIe and Power J7 VGA Front 12 pin 0 079 2mm right angle shrouded header for Video Out J8 LVDS Front 20 pin 0 079 2mm r...

Page 14: ... header for external Gigabit Ethernet LED J27 SMBus Front 5 pin 0 049 1 25mm header for Clock Data and Power I O NOTE The pinout tables in Chapter 3 of this manual identify pin sequence using the following methods A 20 pin header with two rows of pins using odd even numbering where pin 2 is directly across from pin 1 is noted as 20 pin 2 rows odd even 1 2 Alternately a 20 pin connector using conse...

Page 15: ...ck dots on right angle headers indicate pin 2 Table 2 3 Jumper Settings Jumper Installed Removed Installed JP2 LVDS Voltage Select 3 3 Volts Pins 1 2 Default 5 Volts Pins 2 3 JP3 IDE Select Enable HDD master CF slave Pins 1 2 Default Enable HDD slave CF master Pins 2 3 JP4 Compact Flash Voltage Select 5 Volts Pins 1 2 3 3 Volts Pins 2 3 Default JP8 N A For manufacturing only For manufacturing only...

Page 16: ...ension NOTE Height is measured from the upper board surface to the highest permanent component J25 Utility header on the upper board surface This does not include the heatsink Component height should not exceed 0 435 11 05mm from the upper surface of the board and 0 100 2 54mm from the lower surface of the board Weight 0 105 kg 0 232 lbs Height upper surface 10 16mm 0 40 Width 90 170mm 3 550 Lengt...

Page 17: ...quired for this module Thermal Cooling Requirements The CPU is the primary source of heat on the board The CoreModule 730 CPU is designed to operate at maximum speed and requires a heatsink provided NOTE All dimensions are given in inches Pin 1 is shown as a black pin square or round on vertical headers Black dots on right angle headers indicate pin 2 Table 2 5 Power Supply Requirements Parameter ...

Page 18: ...Chapter 2 Product Overview 14 Reference Manual CoreModule 730 ...

Page 19: ...Bus Ethernet LED Watchdog Timer Power Interface NOTE ADLINK Technology Inc only supports the features and options listed in this manual The main components used on the CoreModule 730 may provide more features or options than are listed in this manual Some of these features options are not supported on the module and will not function as specified in the chip documentation The pinout tables only of...

Page 20: ...tem memory controller and the graphics memory controller in the SCH Interrupt Channel Assignments The interrupt channel assignments are shown in Table 3 1 Legend D Default O Optional X Fixed Located on the optional expansion module Table 3 1 Interrupt Channel Assignments Device vs IRQ No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Timer X Keyboard X Secondary Cascade X COM1 O D O O COM2 D O O O COM3 O O...

Page 21: ...S Table 3 2 Memory Map Base Address Function 00000000h 0009FFFFh Conventional Memory 000A0000h 000AFFFFh Graphics Memory 000B0000h 000B7FFFh Mono Text Memory 000B8000h 000BFFFFh Color Text Memory 000C0000h 000CFFFFh Standard Video BIOS 000D0000h 000DFFFFh Reserved for Extended BIOS 000E0000h 000EFFFFh Extended System BIOS Area 000F0000h 000FFFFFh System BIOS Area Storage and RAM Shadowing Top 0 1 ...

Page 22: ...66 Board Controller 0067 NMI Controller 0070 007F CMOS RAM NMI Mask Reg RT Clock 0080 System reserved 0081 0083 System reserved 0084 0086 System reserved 0087 System reserved 0088 System reserved 0089 008B System reserved 008C 008E System reserved 008F System reserved 0090 0091 System reserved 0092 Fast A20 gate and CPU reset 0093 009F System reserved 00A0 00A1 Slave Interrupt Controller 00A2 00BF...

Page 23: ...power or ground 03B0 03BB Video monochrome 03C0 03DF Video VGA 03E8 03EF Serial Port 3 COM3 03F6 IDE Hard Disk Controller 03F8 03FF Serial Port 1 COM1 04D0 04D1 Edge Level Trigger PIC 0778 077F Parallel Port ECP Extensions Port 378 400 0CF8 0CFF PC I Configuration Registers 0CF9 Reset Control Register Table 3 4 USB0 and USB1 Interface Pin Signals J12 Pin Signal Description 1 USB PWR_0 USB0 Power V...

Page 24: ... duplex mode performance is enhanced by a proprietary collision reduction mechanism IEEE 802 3 compatible physical layer to wire transformer IEEE 802 3u Auto Negotiation support Fast back to back transmission support with minimum interframe spacing IFS IEEE 802 3x auto negotiation support for speed and duplex operation 3 kB transmit and 3 kB receive FIFOs helps prevent data underflow and overflow ...

Page 25: ...rt for a maximum pixel format of 24 bpp with SSC supported frequency range from 25 MHz to 112 MHz single channel VGA Interface Table 3 7 describes the pin signals of the VGA interface which uses 12 right angle pins 2 rows odd even sequence 1 2 with 0 079 2mm pitch 5 MDI1 Media Dependent Interface 1 6 MDI1 7 MDI2 Media Dependent Interface 2 8 MDI2 9 MDI3 Media Dependent Interface 3 10 MDI3 NOTE The...

Page 26: ...nnel Data Table 3 8 LVDS Interface Pin Signal Descriptions J8 Pin Signal Description Line 1 VCC_INTRV 12V source 2 VCC_LVDS_CONN JP2 3 3 or 5V source 3 GND Ground Gnd 4 GND Ground 5 LVDS_CLK Clock Positive Output Clk 6 LVDS_CLK Clock Negative Output 7 LVDS_DAT3 Data 3 Positive Output 3 8 LVDS_DAT3 Data 3 Negative Output 9 LVDS_DAT2 Data 2 Positive Output 2 10 LVDS_DAT2 Data 2 Negative Output 11 LV...

Page 27: ... button The system re boots and the BIOS loads the default settings Speaker The speaker signal provides sufficient signal strength to drive a 1W 8 Ω Beep speaker through the Utility interface at an audible level The speaker signal is driven from an on board amplifier and the SCH Note The shaded area denotes power or ground The signals marked with indicate active low Miscellaneous Battery An extern...

Page 28: ... names and corresponding reserved binary addresses on the SMBus Table 3 12 lists the SMBus pin signals on 5 pins 1 row 0 049 2 mm pitch on the external SMBus header J27 Note The shaded areas denote power or ground The signals marked with indicate Negative true logic Table 3 10 User GPIO Interface Pin Signal Descriptions J20 Pin Signal Description 1 H8S_GPI0 User defined 2 H8S_GPO0 User defined 3 H...

Page 29: ...System Operation An application can set up the WDT hardware through a BIOS call or by accessing the hardware directly ADLINK Board Support Packages provide APIs to the WDT The application must tickle reset the WDT before the timer expires or the system will be reset Watchdog Code examples ADLINK has provided source code examples on the CoreModule 730 Support Software QuickDrive illustrating how to...

Page 30: ...nce Manual CoreModule 730 Note The shaded areas denote power or ground 4 12V 12 volts routed to PC 104 5 GND Ground 6 NC Not connected 7 GND Ground 8 5V 5 Volts 9 GND Ground 10 5V 5 Volts Table 3 14 Power Interface Pin Signals J23 ...

Page 31: ...bled through the BIOS Setup Utility The graphical image can be a company logo or any custom image the user wants to display during the boot process The custom image can be displayed as the first image displayed on screen during the boot process and remain there depending on the options selected in BIOS Setup while the OS boots Logo Image Requirements The user s image may be customized with any ima...

Page 32: ...Chapter 4 BIOS Setup 28 Reference Manual CoreModule 730 ...

Page 33: ...ou may also request personal assistance by creating an Ask an Expert account and then going to the Ask a Question feature Requests can be submitted 24 hours a day 7 days a week You will receive immediate confirmation that your request has been entered Once you have submitted your request you must log in to go to My Stuff area where you can check status update your request and access other features...

Page 34: ...Appendix A Technical Support 30 Reference Manual CoreModule 730 ...

Page 35: ...ation 27 Stackable Architecture 3 voltage requirements 25 watchdog timer WDT 25 weight 12 CPU heatsink requirements 13 Intel Atom features 16 D dimensions 12 E Environmental specifications 13 Ethernet controller 20 header 20 supported feature 20 Ethernet chip specifications web sites 2 I Integrated Circuit IC specifications web sites 1 Interrupt IRQs list 16 J Jumper headers locations 11 Jumpers s...

Page 36: ...s 24 Utility header 23 VGA interface 21 video display 5 video interfaces 2 21 watchdog timer WDT 5 25 T Technical Support Ask an Expert 29 contact information 29 InfoCenter 29 thermal cooling heatsinks 13 U USB header pin outs 19 port features 19 Utility header external speaker connection 23 reset switch connection 23 V VGA interface pin out list 21 W Watchdog Timer WDT 1 to 255 settings 25 descri...

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