ADLINK Technology CoreModule 730, Reference Manual

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Chapter 3 Hardware
CoreModule 730 Reference Manual 21
Note: The shaded areas denote power or ground.
Video Interfaces
The SCH chip provides the graphics control and video signals to traditional glass CRT (VGA) monitors and
LVDS flat panel displays, supporting full hardware acceleration of H.264 video decode. Other chip features
are listed below:
VGA features:
•
Support for an integrated 400-MHz, 24-bit RAMDAC to drive a progressive scan analog monitor and
outputs to three, 8-bit DACs that provide the R, G, and B signals to the monitor
•
Support for resolutions up to QXGA (2048x1536)
•
Support for a maximum allowable video frame buffer size of 224MB UMA (Unified Memory
Architecture)
LVDS features:
•
Support for a single channel LFP Transmitter interface
•
Support for LVDS LCD panel resolutions up to UXGA (1600X1200)
•
Support for a maximum pixel format of 24 bpp with SSC supported frequency range from 25 MHz to
112 MHz (single channel)
VGA Interface
Table 3-7 describes the pin signals of the VGA interface, which uses 12 right-angle pins, 2 rows, odd/even
sequence (1, 2) with 0.079" (2mm) pitch.
5 MDI1+ Media Dependent Interface 1 +/-
6 MDI1-
7 MDI2+ Media Dependent Interface 2 +/-
8 MDI2-
9 MDI3+ Media Dependent Interface 3 +/-
10 MDI3-
NOTE The magnetics (isolation transformer, T1) for the Ethernet connector is included
on the CoreModule 730.
Table 3-7. VGA Interface Pin Signals (J7)
Pin # Signal Description
1 RED Red – This is the Red analog output signal to the CRT.
2 GND1 Ground 1 (Red Return)
3 GREEN Green – This is the Green analog output signal to the CRT.
4 GND2 Ground 2 (Green Return)
5 BLUE Blue – This is the Blue analog output signal to the CRT.
6 GND3 Ground 3 (Blue Return)
7 HSYNC Horizontal Sync – This signal is used for the digital horizontal sync
output to the CRT.
8 GND4 Ground 4 (VGA)
Table 3-6. Ethernet Interface Pin/Signal Descriptions (J3) (Continued)