ADLINK Technology CoreModule 730, Reference Manual

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Chapter 3 Hardware
24 Reference Manual CoreModule 730
User GPIO Interface
The CoreModule 730 provides GPIO pins for customer use, and the signals are routed to header J20 which
uses 10 pins with odd/even (1,2) pin sequence and 0.049" (2mm) pitch. An example of how to use the GPIO
pins resides in the Miscellaneous Source Code Examples on the CoreModule 730 Support QuickDrive
TM
.
Note: The shaded areas denote ground.
System Management Bus (SMBus)
The SCH chip contains a host SMBus port. The host port allows the CPU access to the SMBus slaves
through header J27. The SMBus slaves include the SODIMM EPROM, Ethernet controller, CPU
Temperature Sensor, Clock Buffer, and the Clock Generator. Table 3-11 lists the device names and
corresponding reserved binary addresses on the SMBus. Table 3-12 lists the SMBus pin signals on 5 pins, 1
row, 0.049" (2 mm) pitch on the external SMBus header (J27).
Note: The shaded areas denote power or ground. The signals marked with * indicate Negative true logic.
Table 3-10. User GPIO Interface Pin/Signal Descriptions (J20)
Pin # Signal Description
1 H8S_GPI0 User defined
2 H8S_GPO0 User defined
3 H8S_GPI1 User defined
4 H8S_GPO1 User defined
5 H8S_GPI2 User defined
6 H8S_GPO2 User defined
7 H8S_GPI3 User defined
8 H8S_GPO3 User defined
9 GND Ground
10 GND Ground
Table 3-11. SMBus Reserved Addresses
Component Address Binary
SODIMM EPROM 1010,000x
b
Clock Generator 1101,001x
b
Clock Buffer 1101,110x
b
CPU Temperature Sensor 1001,100x
b
Table 3-12. SMBus Pin Signals (J27)
Pin # Signal Description
1 SMB_CLK SMBus Clock
2 GND Ground
3 SMB_DATA SMBus Data
4 VSM +3.3V standby voltage
5 /SMB_ALERT* SMBus Alert