SERIES PMC440 PCI MEZZANINE CARD 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
___________________________________________________________________________________________
- 10 -
registers. Bank 1 allows the 32 event inputs to be monitored and
controlled. Bank 2 registers control the debounce circuitry of the
event inputs. Bits 7 and 6 of this register select the bank as follows:
Bank Selected Status Register (Read)
Bit 7 Bit 6
BANK OF REGISTERS
00
Bank 0 - Read Inputs
01
Bank 1 - Event Status/Clear
10
Bank 2 - Event Debounce Control, Clock, & Duration
11
INVALID - DO NOT WRITE
BANK 2 REGISTERS
Debounce Control Register
(Enhanced Mode Bank 2, Port 0, Read/Write)
This register is used to control whether each individual port is to
be passed through the debounce logic before being recognized by
the circuitry. A “0” disables the debounce logic, and a “1” enables
the debounce logic. Debounce applies to both inputs and event
sense inputs, and only in Enhanced Mode.
Debounce Control Register
BIT
DEBOUNCE CONTROL
“0”
“1”
0
Port 0 (IN00-IN07)
Disable
Enable
1
Port 1 (IN08-IN15)
2
Port 2 (IN16-IN23)
3
Port 3 (IN24-IN31)
4-7
NOT USED
Debounce Duration Register 0
(Enhanced Mode Bank 2, Port 1, Read/Write)
This register controls the duration required by each input signal
before it is recognized by each individual ASIC input in the
Enhanced Mode. Register 0 controls debounce for ports 0-3. If the
debounce clock has been selected (see Debounce Clock Select
Register), then the 8MHz internal system clock will allow the
debounce times shown below to be selected (actual times vary to
within minus 25% of nominal). Note that this time applies to the
ASIC input and does not include the optocoupler time delay.
Debounce Duration Register 0: Duration (8MHz):
BIT
DEBOUNCE CONTROL
Bit 1,0
Time
0
Port 0 Debounce Value Bit 0
00
3-4us
1
Port 0 Debounce Value Bit 1
01
48-64us
2
Port 1 Debounce Value Bit 0
10
0.75-1ms
3
Port 1 Debounce Value Bit 1
11
6-8ms
4
Port 2 Debounce Value Bit 0
5
Port 2 Debounce Value Bit 1
6
Port 3 Debounce Value Bit 0
7
Port 3 Debounce Value Bit 1
Note that with the 8MHz clock enabled, a debounce value of 00
sets 3-4us, 01 sets 48-64us, 10 sets 0.75-1ms, and 11 sets 6-8ms.
The default value is 00, setting a 3-4us debounce period. This
register is cleared following a reset (setting debounce to 3-4us).
Note that the debounce clock must be reselected to re-enable
debounce following a reset (see below).
Debounce Clock Select Register
(Enhanced Mode Bank 2, Port 3, Write Only)
This register selects the source clock for the event sense input
debounce circuitry. If bit 0 of this register is 0 (default value), then
the debounce source clock is disabled. If bit 0 is set to 1, then the
8MHz internal system clock is enabled. This bit must be
programmed to “1” to use debounce. Bits 1-7 of this register are not
used and will always read as zero. This register is cleared following
a reset, disabling use of the 8MHz debounce clock.
Bank Select (Write) & Status (Read) Register 2
(Enhanced Mode Bank 2, Port 7, Read and Write)
Bits 0-5 of this register are not used. Bits 6 & 7 of this register
are used to indicate (read) or select (write) the bank of registers to
be addressed. In Enhanced Mode, three banks (banks 0, 1, & 2) of
eight registers may be addressed. Bank 0 registers are similar to
the Standard Mode bank of registers. Bank 1 allows the 32 event
inputs to be monitored and controlled. Bank 2 registers control the
debounce circuitry of the event inputs. Bits 7 and 6 select/indicate
the bank as follows:
Bank Select (Write) & Status(Read) Register
Bit 7 Bit 6
BANK OF REGISTERS
00
Bank 0 - Read Input Signals
01
Bank 1 - Event Status/Clear
10
Bank 2 - Event Debounce Control, Clock, & Duration
11
INVALID - DO NOT WRITE
INDEPENDENT FIXED FUNCTION CONTROL REGISTERS
Interrupt Enable & Software Reset Register (Read/Write, 23CH)
Bit-0 of this register specifies if the internal event sense
interrupts are to drive INTA# or not. This bit defaults to 0 (interrupt
request disabled) and event interrupts are only flagged internally.
That is, you would have to poll the Event Status Register to
determine if an interrupt had occurred and the INTA# line would not
be driven. If bit-0 of this register is set to “1”, then interrupts will
drive the INTA# line. Note bit-0 of the Interrupt Enable Register is at
Base A 23CH and must always be set to enable interrupts.
This bit is cleared following a system reset, but not a software reset
(see below).
Note, to enable interrupts and the driving of INTA#, you must
also set bit-0 high in the Interrupt Register at Base A000H.
Writing a 1 to the bit-1 position of this register will cause a
software reset to occur (be sure to preserve the current state of bit 0
when conducting a software reset). This bit is not stored and merely
acts as a trigger for software reset generation (this bit will always
readback as 0). The effect of a software reset is similar to a system
reset, except that it only resets the digital ASIC chip that provides
the field interface functions. Likewise, the Interrupt Enable Bit of this
register is not cleared in response to a software reset (these are not
stored in the ASIC). Bits 2-7 of this register are not used and will
always read low (1’s).
THE EFFECT OF RESET
A power-up or bus-initiated software reset will place the module
in the Standard Operating Mode (input only, no event sensing, no
interrupts, and no debounce). A reset will also clear the mask
