SERIES PMC440 PCI MEZZANINE CARD 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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capable of I/O, but this model is intended for input only. A Mask
Register is used to disable writes to I/O ports designed for input
only. Enhanced Mode includes the same functionality of Standard
Mode, but adds access to 32 additional event sense inputs
connected to each input point of ports 0-3. Individual inputs also
include selectable hardware debounce in Enhanced Mode. For
event sensing, the Enhanced Mode allows a specific input level
transition (High-to-Low, Low-to-High, or Change-of-State) to be
detected and optionally generate an interrupt.
Memory is organized and addressed in separate banks of eight
registers or ports (eight ports to a bank). The Standard Mode of
operation addresses the first group of 8 registers or ports (ports 0-3
for reading inputs, Ports 4, 5, & 6 which are not used on this model,
and Port 7 which is the Mask Register). The mask register is
included to mask writes to input points, since the input points of this
model are intended for input only, while the digital ASIC is capable of
output control. If the Enhanced Mode is selected, then 3 additional
banks of 8 registers are accessed to cover the additional
functionality in this mode (events, interrupts, and debounce). The
first bank of the Enhanced Mode (bank 0) is similar in operation to
the Standard Mode. The second bank (bank 1) provides event
sense and interrupt control. The third bank is used to configure the
debounce circuitry to be applied to input channels in the Enhanced
Mode. Two additional mode-independent registers are provided to
enable the interrupt request line, generate a software reset, and
store the interrupt vector.
The memory space address map for the PMC470 is shown in
Table 3.2. Note the base address for the PMC module must be
added to the addresses shown to properly access the PMC
registers. Registers are 8-bit only and are aligned on a 32-bit
boundry. Thus, the 8-bit registers can be accessed over the PCI
bus via 8-bit, 16-bit, or 32-bit accesses. Note that only the lower 8-
bits will contain valid data.
Note that some functions share the same register address. For
these items, the address lines are used along with the read and write
signals to determine the function required.
Standard (Default) Mode Memory Map
The following table shows the memory map for the Standard
Mode of operation. This is the Default mode reached after power-up
or system reset. Standard Mode provides simple monitoring of 32
digital input lines without interrupts. Data is read from or written to
one of eight groups (ports) as designated by the address and read
and write signals. A Mask Register is used to disable writes to input
ports, since this model is intended for input only. That is, the ASIC
used by this model is capable of output, and since this model is
intended for input only, then each port (group of 8 input lines) must
be blocked (masked) from writes.
To switch to Enhanced Mode, four unique bytes must be written
to port 7, in consecutive order, without doing any reads or writes to
any other port and with interrupts disabled. The data pattern to be
written is 07H, 0DH, 06H, and 12H, and this must be written after
reset or power-up.
Table 3.2A: PMC440 R/W Space Address (Hex) Memory Map
Hex
Base
Addr+
MSB
D15 D08
LSB
D07 D00
Hex
Base
Addr+
001
INTERRUPT REGISTER
000
STANDARD MODE (DEFAULT) REGISTER DEFINITIONS:
201
Not Driven
4
READ
1
- Port 0
Register IN00-IN07
200
205
Not Driven
4
READ
1
- Port 1
Register IN08-IN15
204
209
Not Driven
4
READ
1
- Port 2
Register IN16-IN23
208
20D
Not Driven
4
READ
1
- Port 3
Register IN24-IN31
20C
211
Not Driven
4
READ/WRITE
2
- Port 4
NOT USED
210
215
Not Driven
4
READ/WRITE
2
- Port 5
NOT USED
214
219
Not Driven
4
READ/WRITE
2
- Port 6
NOT USED
218
21D
Not Driven
4
READ/WRITE - Port 7
WRITE MASK REGISTER
AND
ENHANCED MODE
SELECT REGISTER
3
21C
221
↓↓↓↓
2FD
NOT USED
5
220
↓↓↓↓
2FC
Notes (Table 3.2A):
1. Writes to these registers are possible, but this model is intended
for input only and writes should not be done. Writes to these
registers may be blocked via the Write Mask Register of Port 7.
2. The ASIC of this model is capable of a greater channel count,
but only 32 channels are used by this model, and as a result,
ports 4, 5, & 6 are not used.
3. Writing four unique bytes (07H, 0DH, 06H, and 12H) to port 7, in
consecutive order, will switch to Enhanced Mode. Do this
without doing any reads or writes to any other port, with
interrupts disabled, and after reset or power-up.
4. Bits 15-8 of these registers are not used. Bits 15-8 will be driven
high (1’s).
5. The PMC will respond to addresses that are "Not Used".
6. Bits 31-16 of these registers will be read (0’s).
Enhanced Mode Memory Maps
The following table shows the memory maps used for the
Enhanced Mode of operation. Enhanced Mode includes the same
functionality of Standard Mode, but allows each input port’s event
sense input and debounce logic to be enabled.
In Enhanced Mode, a memory map is given for each of 3
memory banks. The first memory bank (bank 0) has the same
functionality as the Standard Mode. Additionally, its port 7 register is
used to select which bank to access (similar to Standard Mode
where port 7 was used to select the Enhanced Mode). Bank 1
provides read/write access to the 32 event sense inputs. Bank 2
provides access to the registers used to control the debounce
circuitry of these event sense inputs.
