SERIES PMC440 PCI MEZZANINE CARD 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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Table 3.2B: PMC440 R/W Space Address (Hex) Memory Map
Hex
Base
Addr+
MSB
D15 D08
LSB
D07 D00
Hex
Base
Addr+
001
INTERRUPT REGISTER
000
ENHANCED MODE, REGISTER BANK [0] DEFINITIONS:
201
Not Driven
1
READ
3
- Port 0
Register IN00-IN07
200
205
Not Driven
1
READ
3
-Port 1
Register IN08-IN15
204
209
Not Driven
1
READ
3
- Port 2
Register IN16-IN23
208
20D
Not Driven
1
READ
3
- Port 3
Register IN24-IN31
20C
211
Not Driven
1
READ/WRITE
4
- Port 4
NOT USED
210
215
Not Driven
1
READ/WRITE
4
- Port 5
NOT USED
214
219
Not Driven
1
READ/WRITE
4
- Port 6
NOT USED
218
21D
Not Driven
1
READ - Port 7
READ MASK REGISTER
(Also Current Bank Status)
21C
21D
Not Driven
1
WRITE - Port 7
WRITE MASK REGISTER
(Also Bank Select Register)
21C
ENHANCED MODE, REGISTER BANK [1] DEFINITIONS:
201
Not Driven
1
READ - Port 0
Event Sense Status Reg.
(Port 0 Input points 0-7)
200
201
Not Driven
1
WRITE - Port 0
Event Sense Clear Register
(Port 0 Input points 0-7)
200
205
Not Driven
1
READ - Port 1
Event Sense Status Reg.
(Port 1 Input points 8-15)
204
205
Not Driven
1
WRITE - Port 1
Event Sense Clear Register
(Port 1 Input points 8-15)
204
209
Not Driven
1
READ - Port 2
Event Sense Status Reg.
(Port 2 Input points 16-23)
208
209
Not Driven
1
WRITE - Port 2
Event Sense Clear Register
(Port 2 Input points 16-23)
208
20D
Not Driven
1
READ - Port 3
Event Sense Status Reg.
(Port 3 Input points 24-31)
20C
20D
Not Driven
1
WRITE - Port 3
Event Sense Clear Register
(Port 3 Input points 24-31)
20C
211
Not Driven
1
READ - Port 4
NOT USED
210
211
Not Driven
1
WRITE - Port 4
NOT USED
210
215
Not Driven
1
READ - Port 5
NOT USED
214
215
Not Driven
1
WRITE - Port 5
NOT USED
214
219
Not Driven
1
READ - Port 6
Event Status for Ports 0-3
and Interrupt Status Reg.
218
219
Not Driven
1
WRITE - Port 6
Event Polarity Control
Register for Port 0-3
218
21D
Not Driven
1
READ - Port 7
Current Bank Status Reg.
21C
21D
Not Driven
1
WRITE - Port 7
Bank Select Register
21C
ENHANCED MODE, REGISTER BANK [2] DEFINITIONS:
201
Not Driven
1
READ/WRITE - Port 0
Debounce Control Register
(for Ports 0-3)
200
205
Not Driven
1
READ/WRITE - Port 1
Debounce Duration Reg. 0
(for Ports 0-3)
204
209
Not Driven
1
NOT USED
208
20D
Not Driven
1
WRITE ONLY - Port 3
Debounce Clock Select
20C
211
↓↓↓↓
219
Not Driven
1
Port 4,5,6
NOT USED
2
210
↓↓↓↓
218
21D
Not Driven
1
READ/WRITE - Port 7
Bank Status/Select Register
21C
INDEPENDENT FIXED FUNCTION REGISTERS:
221
↓↓↓↓
239
NOT USED
2
220
↓↓↓↓
238
23D
Not Driven
1
READ/WRITE
Interrupt Enable Register
(Bit 0=1 enables INTREQ0)
& Software Reset Generator
(Bit 1=1 Generates Reset)
23C
241
↓↓↓↓
2FD
NOT USED
2
240
↓↓↓↓
2FC
Notes (Table 3.2B):
1. Bits 15-8 of these registers are not used. Bits 15-8 will be driven
high (1’s).
2. The PMC will respond to addresses that are "Not Used".
3. Writes to these registers are possible, but this model is intended
for input only and writes should not be done. Writes to these
registers may be blocked via the Write Mask Register of Port 7.
4. The ASIC of this model is capable of a greater channel count,
but only 32 channels are used by this model, and as a result,
ports 4, 5, & 6 are not used.
5. Bits 31-16 of these registers will be read as (0’s).
REGISTER DEFINITIONS
Interrupt Register, (Read/Write) - (Base + 00H)
This read/write register is used to: enable board interrupt,
determine the pending status of interrupts, and release an interrupt.
The function of each of the interrupt register bits are described
in Table 3.3. This register can be read or written with either 8-bit,
16-bit, or 32-bit data transfers. A power-up or system reset sets all
interrupt register bits to 0.
