Acromag PMC440 Series User Manual Download Page 11

SERIES PMC440 PCI MEZZANINE CARD                          32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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register and enable writes to the input points of the ASIC (input lines
of this model should be masked from writes).  Further, all event
inputs are reset, set to positive events, and disabled following reset.
A false input signal is ensured for inputs left floating (i.e. reads as
0).  The Interrupt Enable Register (IER) is also cleared (except for
IER generated software resets).

Another form of software reset (IER register initiated) acts

similar to a system or power-up reset, except that it only resets the
digital ASIC chip installed on the module.

PMC440 PROGRAMMING CONSIDERATIONS

To make programming and communicating with the board

easier, Acromag provides a software product (sold separately)
consisting of PMC module VxWorks

 libraries.  This software

(Model PMCSW-API-VXW, MSDOS format) is composed of
VxWorks

 (real time operating system) libraries for all Acromag

PMC modules.  The software is implemented as a library of “C”
functions which link with existing user code to make possible simple
control of all Acromag PMC modules.

Acromag, also provides a software product (sold separately)

consisting of PMC module ActiveX (Object Linking and Embedding)
controls for Windows 98, 95

, ME, 2000 and Windows NT

compatible application programs (Model PMCSW- ATX, MSDOS
format) to program and communicate with the board.

Basic Input Operation

Note that the input lines of this module are assembled in groups

of eight.  Each group of eight lines is referred to as a port.  Ports 0-3
control and monitor input lines 0-31.  Additionally, ports are grouped
eight to a bank.  There are four banks of ports used for controlling
this module (Standard Mode, plus Enhanced Mode Banks 0, 1, and
2), plus 2 additional registers for enabling the interrupt request line,
and generating a software reset.

Each port input line is bipolar and accepts both positive and

negative input voltages in three ranges according to the model
number.  Individual input lines of a port share a common signal
connection with each other.  Separate commons are provided for
each port to facilitate port-to-port isolation.  A high signal is derived
from the absolute value of the input voltage measured between the
input line and the port common for the input ranges of 4-18V
(PMC440-1 models), 16-40V (PMC440-2 models), and 38-60V
(PMC440-3 models).  Inputs are non-inverting and inputs left floating
(not recommended) will register a low (false=0) input indication.

In both the Standard and Enhanced operating modes, each

group of eight parallel input lines (a port) are isolated and gated to
the data bus D0..D7 lines.  A high input will read as “1” and all inputs
include hysteresis and programmable debounce.  Because the ASIC
used by this model is capable of output, individual ports should be
masked from writes to the port since they are intended for input only.

Enhanced Operating Mode

In the Enhanced Mode of operation, each port input may act as

an event sensor and generate interrupts.  Likewise, programmable
debounce logic is also available.  Event sensing is used to
selectively sense high-to-low level, or low-to-high level transitions on
the input lines at the range thresholds of 4V (“-1” units), 16V (“-2”
units), and 38V (“-3” units).  Event polarities may be defined as

positive or negative for individual nibbles (groups of 4 input lines, or
half ports).  Interrupts may also be triggered by events.  The optional
debounce logic can act as a filter to “glitches” or transients present
on received signals.

Because the ASIC used by this model is capable of I/O, while

the module is intended for input only, individual input ports should be
masked from writes to the port.  Otherwise, writing a “1” to an input
line will cause the input to always read 0 (until a “0” is written or a
reset occurs).

The Enhanced Mode is entered by writing four unique bytes to

the Standard Mode Port 7 register, in consecutive order, without
doing any reads or writes to any other ports and with interrupts
disabled.  The data pattern to be written is 07H, 0DH, 06H, and 12H,
and this must be written immediately after reset or power-up.

In Enhanced Mode, there are three groups (or banks) of eight

registers or ports.  The first group, bank 0, provides register
functionality similar to Standard Mode (input level monitoring).  The
second group, bank 1, provides monitor and control of the event
sense inputs.  The third group, bank 2, is used to configure the
debounce circuitry for each input while in the Enhanced Mode.

Event Sensing

The PMC440 has edge-programmable event sense logic built-in

for all 32 input lines, IN00 through IN31.  Event sensing may be
configured to generate an interrupt to the system, or to merely reflect
the interrupt internally.  Event sensing is enabled in Enhanced Mode
only and inputs can be set to detect positive or negative events, on a
nibble-by-nibble (group of 4 input lines) basis.  The event sensing is
enabled on an individual channel basis.  You can combine event
sensing with the built-in debounce control circuitry to obtain “glitch-
free” edge detection of incoming signals.

To program events, determine which input lines are to have

events enabled and which polarity is to be detected, high-to-low level
transitions (negative) or low-to-high level transitions (positive).  Set
each half-port (nibble) to the desired polarity, then enable each of the
event inputs to be detected. Optionally, if interrupt requests are
desired, enable the interrupt request line and set bit 0 of the Interrupt
Register at offset Base A0.  Note that all event inputs are
reset, set to positive events, and disabled after a power-up or
software reset has occured.

Change-Of-State Detection

Change-of-State signal detection requires that both a high-to-low

and low-to-high signal transition be detected.  On the PMC440, if
change-of-state detection for an input signal is desired, two
channels connected to the same input signal would be required--one
sensing positive transitions, one sensing negative transitions.  Since
channel polarity is programmable on a nibble basis (group of four),
the first nibble of a port could be configured for low-to-high
transitions, the second nibble for high-to-low transitions.  As such,
up to 16 change-of-state detectors may be configured.

Debounce Control

Debounce control is built into the on-board digital ASIC

employed by the PMC440 and is enabled in the Enhanced Mode
only. With debounce, an incoming signal must be stable for the
entire debounce time before it is recognized as a valid input or event

Summary of Contents for PMC440 Series

Page 1: ...th Interrupts USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 2000 Acromag Inc Printed in the USA Data and s...

Page 2: ...his is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall system design It is agreed between the Buyer and Acromag th...

Page 3: ...reads writes of registers and the writing of interrupt handlers all the complicated details of programming are handled by the ActiveX controls These functions consist of an ActiveX control for each A...

Page 4: ...of this device are bipolar and may be connected in any direction with respect to the port common Further do not confuse port commons with signal ground Refer to Drawing 4501 869 for example input con...

Page 5: ...software accesses the configuration registers to determine how many blocks of memory space the carrier requires It then programs the PMC module s configuration registers with the unique memory addres...

Page 6: ...pts Data is read from or written to one of eight groups ports as designated by the address and read and write signals A Mask Register is used to disable writes to input ports since this model is inten...

Page 7: ...Driven1 WRITE Port 5 NOT USED 214 219 Not Driven1 READ Port 6 Event Status for Ports 0 3 and Interrupt Status Reg 218 219 Not Driven1 WRITE Port 6 Event Polarity Control Register for Port 0 3 218 21D...

Page 8: ...ite Mask Port 1 Write Mask 2 Port 2 Write Mask Port 2 Write Mask 3 Port 3 Write Mask Port 3 Write Mask 4 7 NOT USED NOT USED Bits 4 7 of this register are not used On power up reset this register defa...

Page 9: ...0 Interrupt Status IN00 IN07 1 Port 1 Interrupt Status IN08 IN15 2 Port 2 Interrupt Status IN16 IN23 3 Port 3 Interrupt Status IN24 IN31 4 6 NOT USED 7 Interrupt Status Flag Event Polarity Control Reg...

Page 10: ...alue then the debounce source clock is disabled If bit 0 is set to 1 then the 8MHz internal system clock is enabled This bit must be programmed to 1 to use debounce Bits 1 7 of this register are not u...

Page 11: ...ow level or low to high level transitions on the input lines at the range thresholds of 4V 1 units 16V 2 units and 38V 3 units Event polarities may be defined as positive or negative for individual ni...

Page 12: ...3CH is cleared following a power up or bus initiated software reset Also bit 0 of the Interrupt Register at Base Address 000H is not affected by a software reset Keep this in mind when you wish to pre...

Page 13: ...if the event sense detection circuitry has been enabled and IER bit 0 1 To enable further interrupts to occur for an event that has already occurred for an I O point the Event Sense Status Register mu...

Page 14: ...at a non functioning board be returned to Acromag for repair The board can be easily damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thor...

Page 15: ...ysteresis 80mV Typical Input Capacitance 45pF Typical Turn On Time Measured to the point of positive event interrupt detection INTA pulled low 15us Typical 25 C for a 0 to threshold value input step T...

Page 16: ...AWG on 0 050 inch centers permits mass termination for IDC connectors foil braided shield inside a PVC jacket Connectors One End SCSI 2 50 pin male connector with backshell and spring latch hardware...

Page 17: ...SERIES PMC440 PCI MEZZANINE CARD 32 CHANNEL ISOLATED DIGITAL INPUT MODULE ___________________________________________________________________________________________ 17...

Page 18: ...SERIES PMC440 PCI MEZZANINE CARD 32 CHANNEL ISOLATED DIGITAL INPUT MODULE ___________________________________________________________________________________________ 18...

Page 19: ...SERIES PMC440 PCI MEZZANINE CARD 32 CHANNEL ISOLATED DIGITAL INPUT MODULE ___________________________________________________________________________________________ 19...

Page 20: ...SERIES PMC440 PCI MEZZANINE CARD 32 CHANNEL ISOLATED DIGITAL INPUT MODULE ___________________________________________________________________________________________ 20...

Page 21: ...SERIES PMC440 PCI MEZZANINE CARD 32 CHANNEL ISOLATED DIGITAL INPUT MODULE ___________________________________________________________________________________________ 21...

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