SERIES PMC440 PCI MEZZANINE CARD 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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- 9 -
Enhanced Mode Bank Select
Bit 7 Bit 6
BANK OF REGISTERS
00
Bank 0 - Read Input Signals
01
Bank 1 - Event Status/Clear
10
Bank 2 - Event Debounce Control, Clock, and
Duration
11
INVALID - DO NOT WRITE
On power-up reset, this device is put into the Standard Mode
and this register defaults to the unmasked state (allowing writes to
the ports which should be avoided), and bank 0 (Default).
BANK 1 REGISTERS
Event Sense Status & Clear Registers For IN00-IN31
(Enhanced Mode Bank 1, Ports 0-3, Read/Write)
Each input line of each port includes an event sense input.
Reading each port will return the status of each input port’s sense
lines. Writing ‘0’ to a bit position of each port will clear the event on
the corresponding line. When writing ports 0-3 of Enhanced Mode
bank 1, each data bit written with a logic 0 clears the corresponding
event sense flip/flop. Further, each data bit of ports 0-3 must be
written with a 1 to re-enable the corresponding event sense input
after it is cleared. Reading ports 0-3 of the Enhanced Mode bank 1
returns the current event sense flip/flop status.
Port 0 Event Sense/Status Register (Ports 1-3 are Similar)
BIT
READ PORT
WRITE “0”
WRITE “1”
0
Port 0 IN00
Event Status
Clear IN00 Event
Sense Flip/Flop
Re-enable IN00
Event Sense
1
Port 0 IN01
Event Status
Clear IN01 Event
Sense Flip/Flop
Re-enable IN01
Event Sense
2
Port 0 IN02
Event Status
Clear IN02 Event
Sense Flip/Flop
Re-enable IN02
Event Sense
3
Port 0 IN03
Event Status
Clear IN03 Event
Sense Flip/Flop
Re-enable IN03
Event Sense
4
Port 0 IN04
Event Status
Clear IN04 Event
Sense Flip/Flop
Re-enable IN04
Event Sense
5
Port 0 IN05
Event Status
Clear IN05 Event
Sense Flip/Flop
Re-enable IN05
Event Sense
6
Port 0 IN06
Event Status
Clear IN06 Event
Sense Flip/Flop
Re-enable IN06
Event Sense
7
Port 0 IN07
Event Status
Clear IN07 Event
Sense Flip/Flop
Re-enable IN07
Event Sense
Event Interrupt Status Register For Ports 0-3
(Enhanced Mode Bank 1, Port 6, Read Only)
Reading this register will return the event interrupt status of
input ports 0-3 (bits 0-3) and the interrupt status flag (bit 7). Bit 7 of
this register indicates an event sense was detected on any of the 4
event sense ports (“1” = interrupt asserted/event sensed). Note that
the interrupt status flag may optionally drive the Interrupt Request
Line of the PMC440 (see Interrupt Enable Register).
Event Interrupt Status Register For Ports 0-3
BIT
READ EVENT STATUS REGISTER
0
Port 0 Interrupt Status (IN00-IN07)
1
Port 1 Interrupt Status (IN08-IN15)
2
Port 2 Interrupt Status (IN16-IN23)
3
Port 3 Interrupt Status (IN24-IN31)
4-6
NOT USED
7
Interrupt Status Flag
Event Polarity Control Register For Ports 0-3
(Enhanced Mode Bank 1, Port 6, Write Only)
A write to this register controls the polarity of the input sense
event for nibbles of ports 0-3 (channels 0-31, four channels at a
time). A “0” written to a bit in this register will cause the
corresponding event sense input lines to flag negative events (high-
to-low transitions). A “1” will cause positive events to be sensed
(low-to-high transitions). The polarity of the event sense logic must
be set prior to enabling the event input logic. Note that no events will
be detected until enabled via the Event Sense Status & Clear
Register. Further, interrupts will not be generated unless the
PMC440 has been enabled via the Interrupt Register.
Event Polarity Control Register
BIT
WRITE “1” (NEGATIVE)
WRITE “0” (POSITIVE)
0
Negative Events on
Port 0 IN00 through IN03
Positive Events on
Port 0 IN00 through IN03
1
Negative Events on
Port 0 IN04 through IN07
Positive Events on
Port 0 IN04 through IN07
2
Negative Events on
Port 1 IN08 through IN11
Positive Events on
Port 1 IN08 through IN11
3
Negative Events on
Port 1 IN12 through IN15
Positive Events on
Port 1 IN12 through IN15
4
Negative Events on
Port 2 IN16 through IN19
Positive Events on
Port 2 IN16 through IN19
5
Negative Events on
Port 2 IN20 through IN23
Positive Events on
Port 2 IN20 through IN23
6
Negative Events on
Port 3 IN24 through IN27
Positive Events on
Port 3 IN24 through IN27
7
Negative Events on
Port 3 IN28 through IN31
Positive Events on
Port 3 IN28 through IN31
Bank Select Register
(Enhanced Mode Bank 1, Port 7, Write Only)
Bits 6 & 7 of this register are used to select/monitor the bank of
registers to be addressed. In Enhanced Mode, three banks (banks
0-2) of eight registers may be addressed. Bank 0 is similar to the
Standard Mode bank of registers. Bank 1 allows the 32 event inputs
to be monitored and controlled. Bank 2 registers control the
debounce circuitry of the event inputs. Bits 0-5 of this register are
not used. Bits 7 and 6 select the bank as follows:
Bank Select Register
BIT
Function
0-5
NOT USED
6
Bank Select Bit 0
7
Bank Select Bit 1
Bank Select Register (Write)
Bit 7 Bit 6
BANK OF REGISTERS
00
Bank 0 - Read Inputs
01
Bank 1 - Event Status/Clear
10
Bank 2 - Event Debounce Control, Clock, and
Duration
11
INVALID - DO NOT WRITE
Bank Select Status Register 1
(Enhanced Mode Bank 1, Port 7, Read Only)
Bits 0-5 of this register are not used. Bits 6 & 7 of this register
are used to indicate the bank of registers to be addressed. In
Enhanced Mode, three banks (banks 0-2) of eight registers may be
addressed. Bank 0 is similar to the Standard Mode bank of
