SERIES PMC440 PCI MEZZANINE CARD 32-CHANNEL ISOLATED DIGITAL INPUT MODULE
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Table 3.3: Interupt Register
BIT
FUNCTION
0
Board Interrupt Enable Bit. This bit must be set to
logic “1” to enable generation of interrupts from the
PMC module. Setting this bit to logic “0” will disable
board interrupts. (Read/Write Bit)
1
Interrupt Pending Status Bit. This bit can be read to
determine the interrupt pending status of the PMC
module. When this bit is logic “1” an interrupt is
pending and will cause an interrupt request if bit-0 of
the register is set. When this bit is a logic “0” an
interrupt is not being requested.
7 to 2
Not Used
1
8
Software Reset
Writing a logic “1” to this bit will cause a reset of PMC
module. Bit-0 of this register will not be affected.
15 to 9
Not Used
1
Notes (Table 3.3):
1. All bits labeled “Not Used” will return logic “0” when read.
STANDARD MODE REGISTERS
Port Registers
(Standard Mode, Ports 0-3, Read, Write Restricted)
Four registers are provided to monitor 32 possible input points.
Data is read from one of four groups of eight input lines (Ports 0-3),
as designated by the address and read and write signals. Each port
assigns the least significant data line (D0) to the least significant
input line of the port grouping (e.g. IN00 for port 0 to D0). A read of
this register returns the status (ON/OFF) of the input point.
Although the ASIC used by this model is capable of output, the
PMC440 is intended for input only and writes to these registers
should be blocked. Writing ‘1’ to this register will cause the input to
always read as 0, and changes in the input will be ignored (until a 0
is written or a reset occurs). A Mask Register is used to disable
writes to ports intended for input only. That is, each port (group of 8
input lines) should be masked from writes.
On power-up or reset, the ports are reset to 0, forcing the
outputs to be set high/OFF (outputs are not used by this model).
Write Mask Register & Enhanced Mode Select Register
(Standard Mode, Port 7, Read/Write)
The ASIC used by the PMC440 is capable of output. However,
the ports of this model are intended for input only and writes to these
ports should be avoided. This register is used to mask the ability to
write data to the four I/O ports of this model. Writing a ‘1’ to bits 0-3
of the Mask Register will mask ports 0-3 respectively, from
inadvertent writes. A read of this register will return the status of the
mask in bits 0-3.
Standard Mode Write Mask Register (Port 7)
BIT
WRITE TO REGISTER
READ FROM REGISTER
0
Port 0 Write Mask
Port 0 Write Mask
1
Port 1 Write Mask
Port 1 Write Mask
2
Port 2 Write Mask
Port 2 Write Mask
3
Port 3 Write Mask
Port 3 Write Mask
4-7
NOT USED
NOT USED
Bits 4-7 of this register are not used. On power-up reset, this
register defaults to the unmasked state, allowing writes to the output
ports.
This register is also used to select the Enhanced Mode of
operation. To switch to Enhanced Mode, four unique bytes must be
written to port 7, in consecutive order, without doing any reads or
writes to any other port and with interrupts disabled. The data
pattern to be written is 07H, 0DH, 06H, and 12H, in order, and this
must be written immediately after reset or power-up.
ENHANCED MODE
BANK 0 REGISTERS
Port Registers
(Enhanced Mode Bank 0, Ports 0-3, Read, Write Restricted)
Four input registers are provided to monitor 32 possible input
points. Data is read from one of four groups (Ports 0-3) of eight
input lines, as designated by the address. Each port assigns the
least significant data line (D0) to the least significant input line of the
port grouping (e.g. IN00 of port 0 to D0). A read of this register
returns the status (ON/OFF) of the input signal. Although the ASIC
used by this model is capable of output, the PMC440 is intended for
input only and writes to these registers should be blocked. Writing
‘1’ to this register will cause the input to always read as 0, and
changes in the input will be ignored (until a 0 is written or a reset
occurs). A Mask Register is used to disable writes to ports intended
for input only. That is, each port (group of 8 input lines) should be
masked from writes (see below).
Write Mask Register And Bank Select Register 0
(Enhanced Mode Bank 0, Port 7, Read/Write)
The ASIC used by the PMC440 is capable of output. However,
the ports of this model are intended for input only and writes to these
ports should be avoided. This register is used to mask the ability to
write data to the four I/O ports of this model. Writing a ‘1’ to bits 0-3
of the Mask Register will mask ports 0-3 respectively, from
inadvertent writes. A read of this register will return the status of the
mask in bits 0-3.
Enhanced Mode Write Mask Register (Port 7)
BIT
WRITE TO REGISTER
READ FROM REGISTER
0
Port 0 Write Mask
Port 0 Write Mask
1
Port 1 Write Mask
Port 1 Write Mask
2
Port 2 Write Mask
Port 2 Write Mask
3
Port 3 Write Mask
Port 3 Write Mask
4-5
NOT USED
NOT USED
6
Bank Select Bit 0
Bank Status Bit 0
7
Bank Select Bit 1
Bank Status Bit 1
Bits 6 & 7 of this register are used to select/monitor the bank of
registers to be addressed. In Enhanced Mode, three banks (banks
0-2) of eight registers may be addressed. Bank 0 registers are
similar to the Standard Mode bank of registers. Bank 1 allows the
32 event inputs to be monitored and controlled. Bank 2 registers
control the debounce circuitry of the event inputs. Bits 7 and 6
select the bank as follows:
